DE60204535D1 - Optimierungsverfahren einer Vielzahl von Tests für digitale integrierte Schaltungen - Google Patents

Optimierungsverfahren einer Vielzahl von Tests für digitale integrierte Schaltungen

Info

Publication number
DE60204535D1
DE60204535D1 DE60204535T DE60204535T DE60204535D1 DE 60204535 D1 DE60204535 D1 DE 60204535D1 DE 60204535 T DE60204535 T DE 60204535T DE 60204535 T DE60204535 T DE 60204535T DE 60204535 D1 DE60204535 D1 DE 60204535D1
Authority
DE
Germany
Prior art keywords
tests
variety
integrated circuits
optimization method
digital integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60204535T
Other languages
English (en)
Other versions
DE60204535T2 (de
Inventor
Kang Wu
Susan L Stirrat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Application granted granted Critical
Publication of DE60204535D1 publication Critical patent/DE60204535D1/de
Publication of DE60204535T2 publication Critical patent/DE60204535T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/31835—Analysis of test coverage or failure detectability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE60204535T 2002-01-15 2002-11-26 Optimierungsverfahren einer Prüfsequenz für digitale integrierte Schaltungen Expired - Lifetime DE60204535T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/047,344 US6941497B2 (en) 2002-01-15 2002-01-15 N-squared algorithm for optimizing correlated events
US47344 2002-01-15

Publications (2)

Publication Number Publication Date
DE60204535D1 true DE60204535D1 (de) 2005-07-14
DE60204535T2 DE60204535T2 (de) 2006-04-27

Family

ID=21948424

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60204535T Expired - Lifetime DE60204535T2 (de) 2002-01-15 2002-11-26 Optimierungsverfahren einer Prüfsequenz für digitale integrierte Schaltungen

Country Status (5)

Country Link
US (1) US6941497B2 (de)
EP (1) EP1327890B1 (de)
JP (1) JP2003232838A (de)
KR (1) KR100966010B1 (de)
DE (1) DE60204535T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040006447A1 (en) * 2000-06-22 2004-01-08 Jacky Gorin Methods and apparatus for test process enhancement
US7395170B2 (en) * 2001-05-24 2008-07-01 Test Advantage, Inc. Methods and apparatus for data analysis
US7167811B2 (en) * 2001-05-24 2007-01-23 Test Advantage, Inc. Methods and apparatus for data analysis
US7225107B2 (en) * 2001-05-24 2007-05-29 Test Advantage, Inc. Methods and apparatus for data analysis
US7904279B2 (en) * 2004-04-02 2011-03-08 Test Advantage, Inc. Methods and apparatus for data analysis
JP4849798B2 (ja) * 2004-12-28 2012-01-11 富士通株式会社 電子機器、記録制御方法及びプログラム
TW200724949A (en) * 2005-08-19 2007-07-01 Koninkl Philips Electronics Nv Test sequence optimization method and design tool
US7596731B1 (en) * 2006-04-07 2009-09-29 Marvell International Ltd. Test time reduction algorithm
US8180142B2 (en) * 2008-12-02 2012-05-15 International Business Machines Corporation Test fail analysis on VLSI chips
US8484592B1 (en) 2012-02-29 2013-07-09 Umm Al-Qura University Timing verification method for circuits
US9401222B1 (en) 2015-11-23 2016-07-26 International Business Machines Corporation Determining categories for memory fail conditions
KR20210047127A (ko) 2019-10-21 2021-04-29 삼성전자주식회사 반도체 회로를 검증하기 위한 최적화된 검증 벡터를 생성하는 전자 장치 및 그 동작 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536802A (ja) * 1991-07-31 1993-02-12 Hitachi Ltd 半導体集積回路補修診断方法
JP2785901B2 (ja) * 1992-03-27 1998-08-13 松下電器産業株式会社 検査系列生成方法および検査系列生成装置
DE69333806T2 (de) 1992-03-27 2005-10-06 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren und Gerät zur Prüfsequenzgenerierung
US5345450A (en) * 1993-03-26 1994-09-06 Vlsi Technology, Inc. Method of compressing and decompressing simulation data for generating a test program for testing a logic device
JPH06282462A (ja) * 1993-03-26 1994-10-07 Toshiba Corp 半導体試験装置制御プログラムデバッグ方式
US5935264A (en) * 1997-06-10 1999-08-10 Micron Technology, Inc. Method and apparatus for determining a set of tests for integrated circuit testing
US6070131A (en) * 1997-09-26 2000-05-30 Micron Technology, Inc. System for evaluating and reporting semiconductor test processes
KR100311013B1 (ko) * 1998-07-04 2001-11-22 윤종용 테스트시퀀스데이터의압축방법
US6810372B1 (en) * 1999-12-07 2004-10-26 Hewlett-Packard Development Company, L.P. Multimodal optimization technique in test generation
US6782501B2 (en) * 2001-01-23 2004-08-24 Cadence Design Systems, Inc. System for reducing test data volume in the testing of logic products

Also Published As

Publication number Publication date
KR20030061686A (ko) 2003-07-22
JP2003232838A (ja) 2003-08-22
US20030140287A1 (en) 2003-07-24
EP1327890A2 (de) 2003-07-16
KR100966010B1 (ko) 2010-06-24
DE60204535T2 (de) 2006-04-27
EP1327890A3 (de) 2003-09-03
EP1327890B1 (de) 2005-06-08
US6941497B2 (en) 2005-09-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: VERIGY (SINGAPORE) PTE. LTD., SINGAPORE, SG