DE602006013515D1 - Verarbeitungseinrichtung durch vorhersage einer abzweigung aus komprimierten adresseninformationen - Google Patents

Verarbeitungseinrichtung durch vorhersage einer abzweigung aus komprimierten adresseninformationen

Info

Publication number
DE602006013515D1
DE602006013515D1 DE602006013515T DE602006013515T DE602006013515D1 DE 602006013515 D1 DE602006013515 D1 DE 602006013515D1 DE 602006013515 T DE602006013515 T DE 602006013515T DE 602006013515 T DE602006013515 T DE 602006013515T DE 602006013515 D1 DE602006013515 D1 DE 602006013515D1
Authority
DE
Germany
Prior art keywords
predicting
distribution
processing device
address information
compressed address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006013515T
Other languages
English (en)
Inventor
Megumi Yokoi
Masaki Ukai
Takashi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE602006013515D1 publication Critical patent/DE602006013515D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE602006013515T 2006-02-28 2006-02-28 Verarbeitungseinrichtung durch vorhersage einer abzweigung aus komprimierten adresseninformationen Active DE602006013515D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/303770 WO2007099605A1 (ja) 2006-02-28 2006-02-28 圧縮したアドレス情報により分岐予測する処理装置

Publications (1)

Publication Number Publication Date
DE602006013515D1 true DE602006013515D1 (de) 2010-05-20

Family

ID=38458729

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006013515T Active DE602006013515D1 (de) 2006-02-28 2006-02-28 Verarbeitungseinrichtung durch vorhersage einer abzweigung aus komprimierten adresseninformationen

Country Status (5)

Country Link
US (1) US7949862B2 (de)
EP (1) EP1990714B1 (de)
JP (1) JP5136405B2 (de)
DE (1) DE602006013515D1 (de)
WO (1) WO2007099605A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008165589A (ja) * 2006-12-28 2008-07-17 Fujitsu Ltd 情報処理装置
JP5678687B2 (ja) * 2011-01-26 2015-03-04 富士通株式会社 処理装置
US8898426B2 (en) 2012-06-11 2014-11-25 International Business Machines Corporation Target buffer address region tracking
JP6179093B2 (ja) * 2012-12-03 2017-08-16 富士通株式会社 演算処理装置、演算処理方法
US10061580B2 (en) * 2016-02-25 2018-08-28 International Business Machines Corporation Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
US10277247B1 (en) * 2018-04-11 2019-04-30 Bae Systems Information And Electronic Systems Integration Inc. Stateful compression scheme for efficient packing of kinematic data
JP7152376B2 (ja) * 2019-09-27 2022-10-12 日本電気株式会社 分岐予測回路、プロセッサおよび分岐予測方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
JP3599409B2 (ja) * 1994-06-14 2004-12-08 株式会社ルネサステクノロジ 分岐予測装置
JP3494736B2 (ja) * 1995-02-27 2004-02-09 株式会社ルネサステクノロジ 分岐先バッファを用いた分岐予測システム
GB9521980D0 (en) 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Branch target buffer
US5701448A (en) * 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
JPH09311787A (ja) * 1996-05-23 1997-12-02 Toshiba Corp データ処理装置
US5938761A (en) * 1997-11-24 1999-08-17 Sun Microsystems Method and apparatus for branch target prediction
US6622241B1 (en) * 2000-02-18 2003-09-16 Hewlett-Packard Development Company, L.P. Method and apparatus for reducing branch prediction table pollution
JP3800533B2 (ja) * 2002-06-28 2006-07-26 富士通株式会社 プログラムカウンタ制御方法及びプロセッサ
JP4052887B2 (ja) * 2002-06-28 2008-02-27 富士通株式会社 記憶装置、分岐履歴記憶装置及びその制御方法
JP3737784B2 (ja) 2002-07-01 2006-01-25 コナミ株式会社 ３次元画像処理プログラム、３次元画像処理方法及びビデオゲーム装置

Also Published As

Publication number Publication date
US7949862B2 (en) 2011-05-24
JPWO2007099605A1 (ja) 2009-07-16
EP1990714A1 (de) 2008-11-12
EP1990714A4 (de) 2009-04-29
JP5136405B2 (ja) 2013-02-06
EP1990714B1 (de) 2010-04-07
WO2007099605A1 (ja) 2007-09-07
US20080313446A1 (en) 2008-12-18

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

8364 No opposition during term of opposition