DE602006007799D1 - Daten-Umstellungsvorrichtung - Google Patents
Daten-UmstellungsvorrichtungInfo
- Publication number
- DE602006007799D1 DE602006007799D1 DE602006007799T DE602006007799T DE602006007799D1 DE 602006007799 D1 DE602006007799 D1 DE 602006007799D1 DE 602006007799 T DE602006007799 T DE 602006007799T DE 602006007799 T DE602006007799 T DE 602006007799T DE 602006007799 D1 DE602006007799 D1 DE 602006007799D1
- Authority
- DE
- Germany
- Prior art keywords
- conversion device
- data conversion
- data
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006050798A JP4814653B2 (ja) | 2006-02-27 | 2006-02-27 | リオーダリング装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006007799D1 true DE602006007799D1 (de) | 2009-08-27 |
Family
ID=37025190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006007799T Active DE602006007799D1 (de) | 2006-02-27 | 2006-06-29 | Daten-Umstellungsvorrichtung |
Country Status (6)
Country | Link |
---|---|
US (1) | US7509482B2 (de) |
EP (1) | EP1826665B1 (de) |
JP (1) | JP4814653B2 (de) |
KR (1) | KR100780306B1 (de) |
CN (1) | CN100559342C (de) |
DE (1) | DE602006007799D1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8341360B2 (en) * | 2005-12-30 | 2012-12-25 | Intel Corporation | Method and apparatus for memory write performance optimization in architectures with out-of-order read/request-for-ownership response |
JP5531513B2 (ja) * | 2009-09-01 | 2014-06-25 | 富士通株式会社 | デスタッフ回路および伝送装置 |
US9524170B2 (en) * | 2013-12-23 | 2016-12-20 | Intel Corporation | Instruction and logic for memory disambiguation in an out-of-order processor |
JP6347681B2 (ja) | 2014-07-01 | 2018-06-27 | キヤノン株式会社 | 情報処理システム、処理装置、画像処理装置、情報処理システムの処理方法及びプログラム |
CN109823628B (zh) * | 2019-01-24 | 2021-01-26 | 中国联合网络通信集团有限公司 | 物体排序整理箱及方法 |
CN115349272A (zh) * | 2020-03-31 | 2022-11-15 | 索尼集团公司 | 解码装置、解码方法、编码装置和编码方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4320466A (en) * | 1979-10-26 | 1982-03-16 | Texas Instruments Incorporated | Address sequence mechanism for reordering data continuously over some interval using a single memory structure |
US5684971A (en) | 1993-12-27 | 1997-11-04 | Intel Corporation | Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions |
JPH08110901A (ja) | 1994-10-12 | 1996-04-30 | Nec Shizuoka Ltd | マイクロプロセッサ |
US6108771A (en) | 1997-12-19 | 2000-08-22 | International Business Machines Corporation | Register renaming with a pool of physical registers |
JP2000048549A (ja) | 1998-08-03 | 2000-02-18 | Fujitsu Ltd | テープ装置 |
US6704856B1 (en) * | 1999-02-01 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Method for compacting an instruction queue |
US6185672B1 (en) * | 1999-02-19 | 2001-02-06 | Advanced Micro Devices, Inc. | Method and apparatus for instruction queue compression |
JP3558001B2 (ja) * | 2000-05-24 | 2004-08-25 | 日本電気株式会社 | 命令バッファ及びバッファキュー制御 |
US6785802B1 (en) * | 2000-06-01 | 2004-08-31 | Stmicroelectronics, Inc. | Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor |
JP3518510B2 (ja) | 2001-01-10 | 2004-04-12 | 日本電気株式会社 | リオーダバッファの管理方法及びプロセッサ |
JP2002304823A (ja) | 2001-04-10 | 2002-10-18 | Fujitsu Ltd | リオーダリングコントローラ、リオーダリング方法及び記憶装置 |
KR20030042289A (ko) | 2001-11-22 | 2003-05-28 | 이용석 | 레지스터 리네이밍 방법을 사용하는 비순차적 명령어 이슈컴퓨터 시스템 |
JP2004135076A (ja) * | 2002-10-10 | 2004-04-30 | Fujitsu Ltd | 断片パケットのリアセンブルおよびリオーダリング装置 |
KR20040082532A (ko) | 2003-03-19 | 2004-09-30 | 주식회사 하이닉스반도체 | 조건부 명령 실행 방법 및 그 방법을 이용하는 비순차적컴퓨터 시스템 |
US7249230B2 (en) | 2004-06-23 | 2007-07-24 | Intel Corporation | Queue structure with validity vector and order array |
-
2006
- 2006-02-27 JP JP2006050798A patent/JP4814653B2/ja not_active Expired - Fee Related
- 2006-06-16 US US11/453,895 patent/US7509482B2/en not_active Expired - Fee Related
- 2006-06-29 DE DE602006007799T patent/DE602006007799D1/de active Active
- 2006-06-29 EP EP06116289A patent/EP1826665B1/de not_active Expired - Fee Related
- 2006-06-30 KR KR1020060061160A patent/KR100780306B1/ko not_active IP Right Cessation
- 2006-07-11 CN CNB2006101015067A patent/CN100559342C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070204136A1 (en) | 2007-08-30 |
JP2007233457A (ja) | 2007-09-13 |
KR20070089026A (ko) | 2007-08-30 |
KR100780306B1 (ko) | 2007-11-29 |
CN101030133A (zh) | 2007-09-05 |
CN100559342C (zh) | 2009-11-11 |
EP1826665B1 (de) | 2009-07-15 |
EP1826665A3 (de) | 2008-05-28 |
US7509482B2 (en) | 2009-03-24 |
EP1826665A2 (de) | 2007-08-29 |
JP4814653B2 (ja) | 2011-11-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8381 | Inventor (new situation) |
Inventor name: KURAMOTO, MASAHIRO, KAWASAKI-SHI, KANAGAWA 211, JP Inventor name: TAKAHASHI, TAKUJI, KAWASAKI-SHI, KANAGAWA 211-, JP |
|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |