DE602006003886D1 - Einrichtung zum schutz eines speichers vor fehlerinjektionsattacken - Google Patents

Einrichtung zum schutz eines speichers vor fehlerinjektionsattacken

Info

Publication number
DE602006003886D1
DE602006003886D1 DE602006003886T DE602006003886T DE602006003886D1 DE 602006003886 D1 DE602006003886 D1 DE 602006003886D1 DE 602006003886 T DE602006003886 T DE 602006003886T DE 602006003886 T DE602006003886 T DE 602006003886T DE 602006003886 D1 DE602006003886 D1 DE 602006003886D1
Authority
DE
Germany
Prior art keywords
battacks
protecting
memory before
fault injection
before fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006003886T
Other languages
English (en)
Inventor
Sylvie Wuidart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Publication of DE602006003886D1 publication Critical patent/DE602006003886D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Storage Device Security (AREA)
  • Static Random-Access Memory (AREA)
DE602006003886T 2005-05-09 2006-03-31 Einrichtung zum schutz eines speichers vor fehlerinjektionsattacken Active DE602006003886D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0504610 2005-05-09
PCT/FR2006/000704 WO2006120310A1 (fr) 2005-05-09 2006-03-31 Dispositif de protection d'une memoire contre les attaques par injection d'erreur

Publications (1)

Publication Number Publication Date
DE602006003886D1 true DE602006003886D1 (de) 2009-01-08

Family

ID=35478348

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006003886T Active DE602006003886D1 (de) 2005-05-09 2006-03-31 Einrichtung zum schutz eines speichers vor fehlerinjektionsattacken

Country Status (5)

Country Link
US (1) US8045381B2 (de)
EP (1) EP1880387B1 (de)
JP (1) JP4920680B2 (de)
DE (1) DE602006003886D1 (de)
WO (1) WO2006120310A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5179923B2 (ja) * 2008-03-31 2013-04-10 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8456926B2 (en) * 2010-11-18 2013-06-04 Grandis, Inc. Memory write error correction circuit
FR2989504B1 (fr) * 2012-04-12 2014-04-25 St Microelectronics Rousset Registre protege contre des attaques par injection de fautes
US9582664B2 (en) 2013-06-11 2017-02-28 Stmicroelectronics (Rousset) Sas Detection of fault injections in a random number generator
CN105227296B (zh) * 2015-10-29 2019-01-25 深圳先进技术研究院 一种抗错误注入攻击的3d密码芯片的制造方法及装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62282392A (ja) * 1986-05-30 1987-12-08 Mitsubishi Electric Corp Ｉｃカ−ド
EP1031992B1 (de) * 1989-04-13 2006-06-21 SanDisk Corporation EEprom-System mit Blocklöschung
US5315700A (en) * 1992-02-18 1994-05-24 Neopath, Inc. Method and apparatus for rapidly processing data sequences
FR2728380A1 (fr) * 1994-12-20 1996-06-21 Sgs Thomson Microelectronics Procede d'ecriture de donnees dans une memoire et memoire electriquement programmable correspondante
US6160734A (en) 1998-06-04 2000-12-12 Texas Instruments Incorporated Method for ensuring security of program data in one-time programmable memory
US6490200B2 (en) * 2000-03-27 2002-12-03 Sandisk Corporation Non-volatile memory with improved sensing and method therefor
JP2000260118A (ja) * 1999-03-11 2000-09-22 Toshiba Corp データ記録メディア、データ記録装置及びデータ読み出し装置
FR2793904B1 (fr) 1999-05-21 2001-07-27 St Microelectronics Sa Procede et dispositif de gestion d'un circuit electronique
JP2001306400A (ja) 2000-04-21 2001-11-02 Sharp Corp 半導体記憶装置、その制御装置、および電子機器
US6839277B2 (en) 2002-09-17 2005-01-04 Silicon Storage Technology, Inc. User identification for multi-purpose flash memory
JP4196770B2 (ja) * 2003-07-23 2008-12-17 ソニー株式会社 データ処理方法、データ検査方法
ITTO20040470A1 (it) * 2004-07-08 2004-10-08 St Microelectronics Srl Circuito di lettura/verifica di celle di memoria multilivello con tensione di lettura a rampa e relativo metodo di lettura/verifica.
FR2874732A1 (fr) * 2004-08-31 2006-03-03 St Microelectronics Sa Procede de programmation de cellules memoire incluant une detection des degradations de transconductance

Also Published As

Publication number Publication date
JP2008541257A (ja) 2008-11-20
JP4920680B2 (ja) 2012-04-18
WO2006120310A1 (fr) 2006-11-16
EP1880387A1 (de) 2008-01-23
US20090073759A1 (en) 2009-03-19
EP1880387B1 (de) 2008-11-26
US8045381B2 (en) 2011-10-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition