DE602005019448D1 - Datenverarbeitungsgerät mit rekonfigurierbarer logischer schaltung - Google Patents

Datenverarbeitungsgerät mit rekonfigurierbarer logischer schaltung

Info

Publication number
DE602005019448D1
DE602005019448D1 DE200560019448 DE602005019448T DE602005019448D1 DE 602005019448 D1 DE602005019448 D1 DE 602005019448D1 DE 200560019448 DE200560019448 DE 200560019448 DE 602005019448 T DE602005019448 T DE 602005019448T DE 602005019448 D1 DE602005019448 D1 DE 602005019448D1
Authority
DE
Germany
Prior art keywords
cycle
data processing
information
pieces
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE200560019448
Other languages
English (en)
Inventor
Hiroki Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
IP Flex Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IP Flex Inc filed Critical IP Flex Inc
Publication of DE602005019448D1 publication Critical patent/DE602005019448D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
DE200560019448 2004-10-28 2005-10-28 Datenverarbeitungsgerät mit rekonfigurierbarer logischer schaltung Active DE602005019448D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004313710 2004-10-28
PCT/JP2005/019924 WO2006046711A1 (ja) 2004-10-28 2005-10-28 再構成可能な論理回路を有するデータ処理装置

Publications (1)

Publication Number Publication Date
DE602005019448D1 true DE602005019448D1 (de) 2010-04-01

Family

ID=36227951

Family Applications (1)

Application Number Title Priority Date Filing Date
DE200560019448 Active DE602005019448D1 (de) 2004-10-28 2005-10-28 Datenverarbeitungsgerät mit rekonfigurierbarer logischer schaltung

Country Status (6)

Country Link
US (3) US7779380B2 (de)
EP (1) EP1806847B1 (de)
JP (1) JP4893309B2 (de)
AT (1) ATE458309T1 (de)
DE (1) DE602005019448D1 (de)
WO (1) WO2006046711A1 (de)

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US8863067B1 (en) 2008-02-06 2014-10-14 Tabula, Inc. Sequential delay analysis by placement engines
US8555218B2 (en) * 2008-05-24 2013-10-08 Tabula, Inc. Decision modules
US8891614B2 (en) * 2008-07-01 2014-11-18 Morphing Machines Pvt Ltd Method and system on chip (SoC) for adapting a runtime reconfigurable hardware to decode a video stream
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WO2011162858A1 (en) 2010-06-23 2011-12-29 Tabula, Inc. Rescaling
US8650514B2 (en) 2010-06-23 2014-02-11 Tabula, Inc. Rescaling
US8941409B2 (en) 2011-07-01 2015-01-27 Tabula, Inc. Configurable storage elements
US8984464B1 (en) 2011-11-21 2015-03-17 Tabula, Inc. Detailed placement with search and repair
US9203397B1 (en) 2011-12-16 2015-12-01 Altera Corporation Delaying start of user design execution
US8789001B1 (en) 2013-02-20 2014-07-22 Tabula, Inc. System and method for using fabric-graph flow to determine resource costs
US9000801B1 (en) 2013-02-27 2015-04-07 Tabula, Inc. Implementation of related clocks
WO2014132670A1 (ja) * 2013-03-01 2014-09-04 アトナープ株式会社 再構成する情報を生成する装置および方法
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US9235669B2 (en) * 2014-02-18 2016-01-12 Codasip S.R.O. Method and an apparatus for automatic processor design and verification
US20160246490A1 (en) * 2015-02-25 2016-08-25 Bank Of America Corporation Customizable Dashboard
US11113091B2 (en) * 2019-03-12 2021-09-07 Arm Limited Apparatus for forwarding a mediated request to processing circuitry in response to a configuration request
WO2023181380A1 (ja) * 2022-03-25 2023-09-28 Ｃｈｉｐｔｉｐ Ｔｅｃｈｎｏｌｏｇｙ株式会社 情報処理システム、情報処理装置、サーバ装置、プログラム、リコンフィグラブルデバイス、又は方法

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US7167025B1 (en) * 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
WO2006046711A1 (ja) 2004-10-28 2006-05-04 Ipflex Inc. 再構成可能な論理回路を有するデータ処理装置
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JP5119902B2 (ja) * 2007-12-19 2013-01-16 富士通セミコンダクター株式会社 動的再構成支援プログラム、動的再構成支援方法、動的再構成回路、動的再構成支援装置および動的再構成システム

Also Published As

Publication number Publication date
EP1806847A4 (de) 2008-02-06
JP4893309B2 (ja) 2012-03-07
ATE458309T1 (de) 2010-03-15
US9135387B2 (en) 2015-09-15
WO2006046711A1 (ja) 2006-05-04
US20080141019A1 (en) 2008-06-12
EP1806847B1 (de) 2010-02-17
US7779380B2 (en) 2010-08-17
US20110004744A1 (en) 2011-01-06
US20140096095A1 (en) 2014-04-03
JPWO2006046711A1 (ja) 2008-05-22
EP1806847A1 (de) 2007-07-11
US8713492B2 (en) 2014-04-29

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Legal Events

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8327 Change in the person/name/address of the patent owner

Owner name: FUJI XEROX CO., LTD., TOKYO, JP

8364 No opposition during term of opposition