DE602005017963D1 - System und Verfahren zur Phasenverriegelung einer Sendertaktsignalphase mit einer Empfängertaktsignalphase - Google Patents
System und Verfahren zur Phasenverriegelung einer Sendertaktsignalphase mit einer EmpfängertaktsignalphaseInfo
- Publication number
- DE602005017963D1 DE602005017963D1 DE602005017963T DE602005017963T DE602005017963D1 DE 602005017963 D1 DE602005017963 D1 DE 602005017963D1 DE 602005017963 T DE602005017963 T DE 602005017963T DE 602005017963 T DE602005017963 T DE 602005017963T DE 602005017963 D1 DE602005017963 D1 DE 602005017963D1
- Authority
- DE
- Germany
- Prior art keywords
- clock signal
- phase
- signal phase
- locking
- transmitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0091—Transmitter details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/813,235 US7545899B2 (en) | 2004-01-30 | 2004-03-31 | System and method of phase-locking a transmit clock signal phase with a receive clock signal phase |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005017963D1 true DE602005017963D1 (de) | 2010-01-14 |
Family
ID=34912658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005017963T Active DE602005017963D1 (de) | 2004-03-31 | 2005-02-17 | System und Verfahren zur Phasenverriegelung einer Sendertaktsignalphase mit einer Empfängertaktsignalphase |
Country Status (5)
Country | Link |
---|---|
US (1) | US7545899B2 (de) |
EP (1) | EP1585247B1 (de) |
CN (1) | CN100446456C (de) |
DE (1) | DE602005017963D1 (de) |
TW (1) | TWI262693B (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7593457B2 (en) * | 2004-01-30 | 2009-09-22 | Broadcom Corporation | Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase |
US7487378B2 (en) * | 2005-09-19 | 2009-02-03 | Ati Technologies, Inc. | Asymmetrical IO method and system |
JP4791158B2 (ja) * | 2005-11-24 | 2011-10-12 | 株式会社日立製作所 | 無線基地局装置および空間多重送信数制御装置 |
US9178713B1 (en) | 2006-11-28 | 2015-11-03 | Marvell International Ltd. | Optical line termination in a passive optical network |
US8208815B1 (en) * | 2006-11-30 | 2012-06-26 | Marvell International Ltd. | Bit accurate upstream burst transmission phase method for reducing burst data arrival variation |
US8321719B2 (en) * | 2009-09-25 | 2012-11-27 | Intel Corporation | Efficient clocking scheme for a bidirectional data link |
US8488657B2 (en) * | 2010-06-04 | 2013-07-16 | Maxim Integrated Products, Inc. | Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters |
US8891561B2 (en) * | 2012-07-16 | 2014-11-18 | Broadcom Corporation | 50 Gb/s ethernet using serializer/deserializer lanes |
US8873606B2 (en) * | 2012-11-07 | 2014-10-28 | Broadcom Corporation | Transceiver including a high latency communication channel and a low latency communication channel |
US9225344B2 (en) * | 2013-01-16 | 2015-12-29 | Altera Corporation | Methods and apparatus for aligning clock signals on an integrated circuit |
JP2017011342A (ja) * | 2015-06-16 | 2017-01-12 | 富士通株式会社 | 伝送装置及びクロック再生方法 |
US11038602B1 (en) * | 2020-02-05 | 2021-06-15 | Credo Technology Group Limited | On-chip jitter evaluation for SerDes |
US10992501B1 (en) | 2020-03-31 | 2021-04-27 | Credo Technology Group Limited | Eye monitor for parallelized digital equalizers |
US10892763B1 (en) * | 2020-05-14 | 2021-01-12 | Credo Technology Group Limited | Second-order clock recovery using three feedback paths |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5434719A (en) | 1994-03-18 | 1995-07-18 | Seagate Technology, Inc. | Correction of header information in a magnetic disc drive |
JPH09247140A (ja) * | 1996-03-08 | 1997-09-19 | Mitsubishi Electric Corp | インタコネクション装置 |
US6643787B1 (en) * | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
WO2002089405A2 (en) | 2001-04-27 | 2002-11-07 | The Boeing Company | Fibre channel transceiver |
US6798784B2 (en) | 2001-06-04 | 2004-09-28 | Caux Networks, Inc. | Concurrent switching of synchronous and asynchronous traffic |
US7158587B2 (en) | 2001-09-18 | 2007-01-02 | Agere Systems Inc. | Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof |
US7155006B2 (en) * | 2001-09-21 | 2006-12-26 | Intel Corporation | Method and apparatus for outbound wave subtraction using a variable offset amplifier |
US7286487B2 (en) | 2002-11-18 | 2007-10-23 | Infinera Corporation | Optical transmission network with asynchronous mapping and demapping and digital wrapper frame for the same |
US6650141B2 (en) | 2001-12-14 | 2003-11-18 | Lattice Semiconductor Corporation | High speed interface for a programmable interconnect circuit |
JP2003244085A (ja) * | 2002-02-19 | 2003-08-29 | Fujitsu Ltd | 複数系統伝送路における位相合致制御システム及び位相合致制御方法 |
US7191371B2 (en) | 2002-04-09 | 2007-03-13 | Internatioanl Business Machines Corporation | System and method for sequential testing of high speed serial link core |
US7587587B2 (en) | 2002-12-05 | 2009-09-08 | Broadcom Corporation | Data path security processing |
JP4257830B2 (ja) | 2003-03-11 | 2009-04-22 | パナソニック株式会社 | データ送受信装置 |
TWI235922B (en) | 2003-03-13 | 2005-07-11 | Via Tech Inc | Circuit structure of separated serial ATA physical layer and signal encoding method |
US7133648B1 (en) | 2003-06-03 | 2006-11-07 | Xilinx, Inc. | Bidirectional multi-gigabit transceiver |
US7280612B2 (en) * | 2003-07-25 | 2007-10-09 | Zarbana Digital Fund Llc | Digital branch calibrator for an RF transmitter |
US7486718B2 (en) * | 2003-08-04 | 2009-02-03 | Marvell International Ltd. | Architectures, circuits, systems and methods for reducing latency in data communications |
US7436777B2 (en) | 2004-01-12 | 2008-10-14 | Hewlett-Packard Development Company, L.P. | Failed link training |
US7424076B2 (en) * | 2004-01-22 | 2008-09-09 | Nokia Corporation | System and method for providing synchronization information to a receiver |
US7430203B2 (en) | 2004-01-29 | 2008-09-30 | Brocade Communications Systems, Inc. | Fibre channel zoning hardware for directing a data packet to an external processing device |
US7593457B2 (en) | 2004-01-30 | 2009-09-22 | Broadcom Corporation | Transceiver system and method having a transmit clock signal phase that is phase-locked with a receive clock signal phase |
-
2004
- 2004-03-31 US US10/813,235 patent/US7545899B2/en active Active
-
2005
- 2005-02-17 EP EP05003406A patent/EP1585247B1/de not_active Expired - Fee Related
- 2005-02-17 DE DE602005017963T patent/DE602005017963D1/de active Active
- 2005-03-28 CN CNB2005100625973A patent/CN100446456C/zh not_active Expired - Fee Related
- 2005-03-30 TW TW094110002A patent/TWI262693B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1585247B1 (de) | 2009-12-02 |
TWI262693B (en) | 2006-09-21 |
TW200610343A (en) | 2006-03-16 |
US7545899B2 (en) | 2009-06-09 |
CN1677916A (zh) | 2005-10-05 |
EP1585247A3 (de) | 2006-04-19 |
US20050169417A1 (en) | 2005-08-04 |
EP1585247A2 (de) | 2005-10-12 |
CN100446456C (zh) | 2008-12-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |