DE602005015422D1 - Integrierter schaltungschip mit kommunikationsmitteln, wodurch eine fernbedienung von testmitteln von ip-kernen der integrierten schaltung möglich wird - Google Patents

Integrierter schaltungschip mit kommunikationsmitteln, wodurch eine fernbedienung von testmitteln von ip-kernen der integrierten schaltung möglich wird

Info

Publication number
DE602005015422D1
DE602005015422D1 DE602005015422T DE602005015422T DE602005015422D1 DE 602005015422 D1 DE602005015422 D1 DE 602005015422D1 DE 602005015422 T DE602005015422 T DE 602005015422T DE 602005015422 T DE602005015422 T DE 602005015422T DE 602005015422 D1 DE602005015422 D1 DE 602005015422D1
Authority
DE
Germany
Prior art keywords
integrated circuit
testants
schip
core
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005015422T
Other languages
English (en)
Inventor
Oussama Laouamri
Chouki Aktouf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institut Polytechnique de Grenoble
Original Assignee
Institut Polytechnique de Grenoble
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut Polytechnique de Grenoble filed Critical Institut Polytechnique de Grenoble
Publication of DE602005015422D1 publication Critical patent/DE602005015422D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318508—Board Level Test, e.g. P1500 Standard
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE602005015422T 2004-02-17 2005-02-17 Integrierter schaltungschip mit kommunikationsmitteln, wodurch eine fernbedienung von testmitteln von ip-kernen der integrierten schaltung möglich wird Active DE602005015422D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54431904P 2004-02-17 2004-02-17
PCT/EP2005/001629 WO2005078465A1 (en) 2004-02-17 2005-02-17 Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit

Publications (1)

Publication Number Publication Date
DE602005015422D1 true DE602005015422D1 (de) 2009-08-27

Family

ID=34860501

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005015422T Active DE602005015422D1 (de) 2004-02-17 2005-02-17 Integrierter schaltungschip mit kommunikationsmitteln, wodurch eine fernbedienung von testmitteln von ip-kernen der integrierten schaltung möglich wird

Country Status (5)

Country Link
US (1) US7725784B2 (de)
EP (1) EP1716424B1 (de)
JP (1) JP2007524947A (de)
DE (1) DE602005015422D1 (de)
WO (1) WO2005078465A1 (de)

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JP2009512873A (ja) * 2005-10-24 2009-03-26 エヌエックスピー ビー ヴィ Ｉｃのテスト方法及び装置
JP5171632B2 (ja) * 2005-10-24 2013-03-27 エヌエックスピー ビー ヴィ Ｉｃテスト方法及びその装置
CN101297207B (zh) * 2005-10-24 2012-03-28 Nxp股份有限公司 Ic测试方法及设备
WO2007069097A1 (en) * 2005-11-02 2007-06-21 Nxp B.V. Ic testing methods and apparatus
EP1811415A1 (de) * 2005-12-23 2007-07-25 Nagracard S.A. Sicheres System-on-Chip
US8656191B2 (en) 2005-12-23 2014-02-18 Nagravision S.A. Secure system-on-chip
EP1802030A1 (de) * 2005-12-23 2007-06-27 Nagracard S.A. Sicheres System-on-Chip
US7827517B1 (en) * 2006-05-19 2010-11-02 Altera Corporation Automated register definition, builder and integration framework
US7519884B2 (en) 2006-06-16 2009-04-14 Texas Instruments Incorporated TAM controller for plural test access mechanisms
US7908531B2 (en) 2006-09-29 2011-03-15 Teradyne, Inc. Networked test system
US8421587B2 (en) 2007-04-26 2013-04-16 Freescale Semiconductor, Inc. Diagnosis for mixed signal device for use in a distributed system
PT103744A (pt) * 2007-05-16 2008-11-17 Coreworks S A Arquitectura de acesso ao núcleo de rede.
US7949915B2 (en) * 2007-12-04 2011-05-24 Alcatel-Lucent Usa Inc. Method and apparatus for describing parallel access to a system-on-chip
US7962885B2 (en) * 2007-12-04 2011-06-14 Alcatel-Lucent Usa Inc. Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing
US7958479B2 (en) 2007-12-04 2011-06-07 Alcatel-Lucent Usa Inc. Method and apparatus for describing and testing a system-on-chip
CN101232456B (zh) * 2008-01-25 2010-09-08 浙江大学 一种分布式可测试片上网络路由器
US7954022B2 (en) 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
US7958417B2 (en) 2008-01-30 2011-06-07 Alcatel-Lucent Usa Inc. Apparatus and method for isolating portions of a scan path of a system-on-chip
EP2387723B1 (de) 2009-01-15 2014-09-17 Electronic Warfare Associates, Inc. Systeme und verfahren zum implementieren von fern-boundary-scan-merkmalen
US8447969B2 (en) * 2009-03-13 2013-05-21 Assa Abloy Ab Transfer device for sensitive material such as a cryptographic key
US9032058B2 (en) 2009-03-13 2015-05-12 Assa Abloy Ab Use of SNMP for management of small footprint devices
US8332498B2 (en) 2009-03-13 2012-12-11 Assa Abloy Ab Synchronized relay messaging and coordinated network processing using SNMP
US20100235900A1 (en) * 2009-03-13 2010-09-16 Assa Abloy Ab Efficient two-factor authentication
EP2228746A1 (de) * 2009-03-13 2010-09-15 Assa Abloy Ab Realisierung von Zugriffssteuerungszuständen als Boolesche Ausdrücke bei Passwortauthentifizierungen
EP2406718A4 (de) 2009-03-13 2012-08-15 Assa Abloy Ab Sicheres kartenzugangsmodul für chipkartenanwendungen
EP2372379B1 (de) * 2010-03-26 2013-01-23 Imec Testzugriffsarchitektur für TSV-basierte 3D-gestapelte ICS
US8397188B1 (en) * 2010-09-21 2013-03-12 Altera Corporation Systems and methods for testing a component by using encapsulation
US8694276B2 (en) * 2011-01-20 2014-04-08 Texas Instruments Incorporated Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure
US8522189B2 (en) * 2011-03-09 2013-08-27 Intel Corporation Functional fabric based test access mechanism for SoCs
US9043665B2 (en) 2011-03-09 2015-05-26 Intel Corporation Functional fabric based test wrapper for circuit testing of IP blocks
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TWI546692B (zh) 2011-10-27 2016-08-21 電子戰協會公司 包括與已知電路板資訊有關之電路測試及驗證等特徵的裝置鑑別之系統及方法
US20150067428A1 (en) * 2012-05-02 2015-03-05 Freescale Semiconductor, Inc. System-on-chip, method of manufacture thereof and method of communicating diagnostic data
US8694951B1 (en) 2012-10-02 2014-04-08 Lsi Corporation Core wrapping in the presence of an embedded wrapped core
US8643168B1 (en) 2012-10-16 2014-02-04 Lattice Semiconductor Corporation Integrated circuit package with input capacitance compensation
US8732632B1 (en) * 2013-03-15 2014-05-20 Cadence Design Systems, Inc. Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test
US10481203B2 (en) 2015-04-04 2019-11-19 Nvidia Corporation Granular dynamic test systems and methods
US9477807B1 (en) 2015-06-11 2016-10-25 International Business Machines Corporation Automating system on a chip customized design integration, specification, and verification through a single, integrated service
US10281524B2 (en) * 2015-10-27 2019-05-07 Nvidia Corporation Test partition external input/output interface control for test partitions in a semiconductor
US10698805B1 (en) * 2017-01-25 2020-06-30 Cadence Design Systems, Inc. Method and system for profiling performance of a system on chip
US11408934B2 (en) 2017-12-22 2022-08-09 Nvidia Corporation In system test of chips in functional systems
US11366777B2 (en) * 2019-06-11 2022-06-21 Honeywell International, Inc. Process control device having modern architecture and legacy compatibility
US11269999B2 (en) * 2019-07-01 2022-03-08 At&T Intellectual Property I, L.P. Protecting computing devices from malicious tampering
US11250167B2 (en) * 2019-09-26 2022-02-15 Intel Corporation Secure external SoC debugging
CN114443375A (zh) * 2020-11-04 2022-05-06 富泰华工业（深圳）有限公司 测试方法及装置、电子装置及计算机可读存储介质
CN114650246A (zh) * 2020-12-18 2022-06-21 中国移动通信有限公司研究院 Ip核调用的检测方法、装置及设备
CN116298799B (zh) * 2023-03-10 2024-03-19 深圳市晶存科技有限公司 芯片测试多界面联动显示方法及系统

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US6877122B2 (en) * 2001-12-21 2005-04-05 Texas Instruments Incorporated Link instruction register providing test control signals to core wrappers
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US7437635B1 (en) * 2003-12-30 2008-10-14 Altera Corporation Testing hard-wired IP interface signals using a soft scan chain

Also Published As

Publication number Publication date
US20080034334A1 (en) 2008-02-07
US7725784B2 (en) 2010-05-25
WO2005078465A1 (en) 2005-08-25
EP1716424B1 (de) 2009-07-15
JP2007524947A (ja) 2007-08-30
EP1716424A1 (de) 2006-11-02

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