DE602005007633D1 - Wärmegeregelte, fluidische selbstmontage - Google Patents

Wärmegeregelte, fluidische selbstmontage

Info

Publication number
DE602005007633D1
DE602005007633D1 DE602005007633T DE602005007633T DE602005007633D1 DE 602005007633 D1 DE602005007633 D1 DE 602005007633D1 DE 602005007633 T DE602005007633 T DE 602005007633T DE 602005007633 T DE602005007633 T DE 602005007633T DE 602005007633 D1 DE602005007633 D1 DE 602005007633D1
Authority
DE
Germany
Prior art keywords
assembly
thermal control
fluid self
self
fluid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005007633T
Other languages
English (en)
Inventor
Ravi Sharma
Charles P Lusignan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of DE602005007633D1 publication Critical patent/DE602005007633D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95053—Bonding environment
    • H01L2224/95085—Bonding environment being a liquid, e.g. for fluidic self-assembly
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95136—Aligning the plurality of semiconductor or solid-state bodies involving guiding structures, e.g. shape matching, spacers or supporting members
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H01L2224/95144—Magnetic alignment, i.e. using permanent magnetic parts in the semiconductor or solid-state body
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
    • H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H01L2224/95145—Electrostatic alignment, i.e. polarity alignment with Coulomb charges
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
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    • H01L2924/15165—Monolayer substrate
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    • H01L2924/1901—Structure
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    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/19042—Component type being an inductor
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T436/00—Chemistry: analytical and immunological testing
    • Y10T436/25—Chemistry: analytical and immunological testing including sample preparation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
  • Micromachines (AREA)
DE602005007633T 2004-12-22 2005-12-20 Wärmegeregelte, fluidische selbstmontage Active DE602005007633D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/021,120 US7687277B2 (en) 2004-12-22 2004-12-22 Thermally controlled fluidic self-assembly
PCT/US2005/046316 WO2006069137A1 (en) 2004-12-22 2005-12-20 Thermally controlled fluidic self-assembly

Publications (1)

Publication Number Publication Date
DE602005007633D1 true DE602005007633D1 (de) 2008-07-31

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DE602005007633T Active DE602005007633D1 (de) 2004-12-22 2005-12-20 Wärmegeregelte, fluidische selbstmontage

Country Status (5)

Country Link
US (2) US7687277B2 (de)
EP (1) EP1829104B1 (de)
JP (1) JP4990794B2 (de)
DE (1) DE602005007633D1 (de)
WO (1) WO2006069137A1 (de)

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US7687277B2 (en) 2010-03-30
WO2006069137A1 (en) 2006-06-29
JP2008525206A (ja) 2008-07-17
US20100122654A1 (en) 2010-05-20
JP4990794B2 (ja) 2012-08-01
EP1829104B1 (de) 2008-06-18
EP1829104A1 (de) 2007-09-05

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