DE602005002774D1 - Ein verbesserter on-chip Speicher zur Speicherung von variablen Datenbits - Google Patents

Ein verbesserter on-chip Speicher zur Speicherung von variablen Datenbits

Info

Publication number
DE602005002774D1
DE602005002774D1 DE602005002774T DE602005002774T DE602005002774D1 DE 602005002774 D1 DE602005002774 D1 DE 602005002774D1 DE 602005002774 T DE602005002774 T DE 602005002774T DE 602005002774 T DE602005002774 T DE 602005002774T DE 602005002774 D1 DE602005002774 D1 DE 602005002774D1
Authority
DE
Germany
Prior art keywords
improved
data bits
variable data
chip memory
storing variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005002774T
Other languages
English (en)
Inventor
Swapnil Bahl
Balwant Singh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Pvt Ltd
Original Assignee
STMicroelectronics Pvt Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Pvt Ltd filed Critical STMicroelectronics Pvt Ltd
Publication of DE602005002774D1 publication Critical patent/DE602005002774D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
DE602005002774T 2004-04-08 2005-04-06 Ein verbesserter on-chip Speicher zur Speicherung von variablen Datenbits Active DE602005002774D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN694DE2004 2004-04-08

Publications (1)

Publication Number Publication Date
DE602005002774D1 true DE602005002774D1 (de) 2007-11-22

Family

ID=34897738

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005002774T Active DE602005002774D1 (de) 2004-04-08 2005-04-06 Ein verbesserter on-chip Speicher zur Speicherung von variablen Datenbits

Country Status (3)

Country Link
US (1) US7372755B2 (de)
EP (1) EP1585024B1 (de)
DE (1) DE602005002774D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100299996A1 (en) * 2008-03-20 2010-12-02 Pfefferle William C Method for high efficiency for producing fuel gas for power generation
US8300479B2 (en) * 2010-03-25 2012-10-30 Infinera Corporation Temporal alignment of data unit groups in a switch

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420984A (en) * 1992-06-30 1995-05-30 Genroco, Inc. Apparatus and method for rapid switching between control of first and second DMA circuitry to effect rapid switching beween DMA communications
JP3086769B2 (ja) * 1993-09-29 2000-09-11 株式会社東芝 マルチポートフィールドメモリ
WO1996009627A1 (de) * 1994-09-23 1996-03-28 OCé PRINTING SYSTEMS GMBH Speichereinrichtung und verfahren zum gleichzeitigen lesendund schreiben von daten
US5487049A (en) * 1994-11-23 1996-01-23 Samsung Semiconductor, Inc. Page-in, burst-out FIFO
US5784700A (en) * 1994-12-12 1998-07-21 Texas Instruments Incorporated Memory interface with address shift for different memory types
KR0172238B1 (ko) * 1995-06-30 1999-03-30 김주용 멀티-비트 데이타 출력 완충장치
US5787454A (en) * 1995-12-27 1998-07-28 Intel Corporation Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array
GB9606927D0 (en) * 1996-04-02 1996-06-05 Memory Corp Plc Data storage devices
US6026032A (en) * 1998-08-31 2000-02-15 Genroco, Inc. High speed data buffer using a virtual first-in-first-out register
US6424591B1 (en) * 1999-05-28 2002-07-23 Advanced Micro Devices, Inc. Network interface supporting fifo-type and SRAM-type accesses to internal buffer memory
JP3776295B2 (ja) * 2000-06-26 2006-05-17 沖電気工業株式会社 シリアルアクセスメモリおよびデータライト／リード方法

Also Published As

Publication number Publication date
US20050232028A1 (en) 2005-10-20
US7372755B2 (en) 2008-05-13
EP1585024A1 (de) 2005-10-12
EP1585024B1 (de) 2007-10-10

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Legal Events

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