DE602004005200D1 - Offset abhängiger Widerstand zur Messung der Fehlausrichtung zusammengefügter Masken - Google Patents

Offset abhängiger Widerstand zur Messung der Fehlausrichtung zusammengefügter Masken

Info

Publication number
DE602004005200D1
DE602004005200D1 DE602004005200T DE602004005200T DE602004005200D1 DE 602004005200 D1 DE602004005200 D1 DE 602004005200D1 DE 602004005200 T DE602004005200 T DE 602004005200T DE 602004005200 T DE602004005200 T DE 602004005200T DE 602004005200 D1 DE602004005200 D1 DE 602004005200D1
Authority
DE
Germany
Prior art keywords
dependent resistor
offset dependent
circuit
resistor structure
measuring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004005200T
Other languages
English (en)
Other versions
DE602004005200T2 (de
Inventor
Joseph M Amato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE602004005200D1 publication Critical patent/DE602004005200D1/de
Application granted granted Critical
Publication of DE602004005200T2 publication Critical patent/DE602004005200T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228Resistive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
DE602004005200T 2003-06-25 2004-06-25 Offset abhängiger Widerstand zur Messung der Fehlausrichtung zusammengefügter Masken Expired - Lifetime DE602004005200T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US48227803P 2003-06-25 2003-06-25
US482278P 2003-06-25
PCT/US2004/020573 WO2005004238A2 (en) 2003-06-25 2004-06-25 Offset dependent resistor for measuring misalignment of stitched masks

Publications (2)

Publication Number Publication Date
DE602004005200D1 true DE602004005200D1 (de) 2007-04-19
DE602004005200T2 DE602004005200T2 (de) 2007-11-15

Family

ID=33563843

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004005200T Expired - Lifetime DE602004005200T2 (de) 2003-06-25 2004-06-25 Offset abhängiger Widerstand zur Messung der Fehlausrichtung zusammengefügter Masken

Country Status (7)

Country Link
US (1) US7538443B2 (de)
EP (1) EP1642337B1 (de)
JP (1) JP2007526497A (de)
CN (1) CN100477203C (de)
AT (1) ATE356437T1 (de)
DE (1) DE602004005200T2 (de)
WO (1) WO2005004238A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009539421A (ja) * 2006-06-02 2009-11-19 ダブリューエムエス・ゲイミング・インコーポレーテッド ハンドヘルド賭け事ゲームシステム及びこのゲームシステム上で賭け事ゲームを実施する方法
GB2533967B (en) * 2015-01-12 2021-08-25 Advanced Risc Mach Ltd Adapting the usage configuration of integrated circuit input-output pads
CN105241367A (zh) * 2015-10-26 2016-01-13 上海华力微电子有限公司 一种缝合工艺对准精度的检测方法及结构
US10930571B2 (en) 2019-02-01 2021-02-23 Samsung Electronics Co., Ltd. Test structure and evaluation method for semiconductor photo overlay
CN110058486B (zh) * 2019-03-26 2022-06-28 云谷(固安)科技有限公司 掩膜板组件及掩膜板组件拼接精度的检测方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808527A (en) 1973-06-28 1974-04-30 Ibm Alignment determining system
JP3552077B2 (ja) 1996-07-26 2004-08-11 ソニー株式会社 合わせずれ測定方法及び合わせずれ測定パターン
US5898228A (en) 1997-10-03 1999-04-27 Lsi Logic Corporation On-chip misalignment indication
US5998226A (en) 1998-04-02 1999-12-07 Lsi Logic Corporation Method and system for alignment of openings in semiconductor fabrication
US6305905B1 (en) * 1999-05-05 2001-10-23 United Technologies Corporation Bolted-on propeller blade
US6305095B1 (en) 2000-02-25 2001-10-23 Xilinx, Inc. Methods and circuits for mask-alignment detection
US6393714B1 (en) 2000-02-25 2002-05-28 Xilinx, Inc. Resistor arrays for mask-alignment detection
US6323097B1 (en) 2000-06-09 2001-11-27 Taiwan Semiconductor Manufacturing Company Electrical overlay/spacing monitor method using a ladder resistor

Also Published As

Publication number Publication date
EP1642337A2 (de) 2006-04-05
WO2005004238A3 (en) 2005-07-07
WO2005004238A2 (en) 2005-01-13
ATE356437T1 (de) 2007-03-15
US20070030335A1 (en) 2007-02-08
CN100477203C (zh) 2009-04-08
JP2007526497A (ja) 2007-09-13
CN1809924A (zh) 2006-07-26
EP1642337B1 (de) 2007-03-07
DE602004005200T2 (de) 2007-11-15
US7538443B2 (en) 2009-05-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN