DE60143469D1 - Arithmetische Schaltung und Verfahren zur Produktsummenberechnung - Google Patents

Arithmetische Schaltung und Verfahren zur Produktsummenberechnung

Info

Publication number
DE60143469D1
DE60143469D1 DE60143469T DE60143469T DE60143469D1 DE 60143469 D1 DE60143469 D1 DE 60143469D1 DE 60143469 T DE60143469 T DE 60143469T DE 60143469 T DE60143469 T DE 60143469T DE 60143469 D1 DE60143469 D1 DE 60143469D1
Authority
DE
Germany
Prior art keywords
arithmetic circuit
sum calculation
product sum
product
calculation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60143469T
Other languages
English (en)
Inventor
Masayuki Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Application granted granted Critical
Publication of DE60143469D1 publication Critical patent/DE60143469D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
DE60143469T 2001-01-31 2001-09-05 Arithmetische Schaltung und Verfahren zur Produktsummenberechnung Expired - Lifetime DE60143469D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001024153A JP3935678B2 (ja) 2001-01-31 2001-01-31 Ｓｉｍｄ積和演算方法、積和演算回路、および、半導体集積回路装置

Publications (1)

Publication Number Publication Date
DE60143469D1 true DE60143469D1 (de) 2010-12-30

Family

ID=18889336

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60143469T Expired - Lifetime DE60143469D1 (de) 2001-01-31 2001-09-05 Arithmetische Schaltung und Verfahren zur Produktsummenberechnung

Country Status (4)

Country Link
US (1) US7043519B2 (de)
EP (1) EP1229438B1 (de)
JP (1) JP3935678B2 (de)
DE (1) DE60143469D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670895B2 (en) * 2002-05-01 2003-12-30 Analog Devices, Inc. Method and apparatus for swapping the contents of address registers
US7275147B2 (en) 2003-03-31 2007-09-25 Hitachi, Ltd. Method and apparatus for data alignment and parsing in SIMD computer architecture
US20060224652A1 (en) * 2005-04-05 2006-10-05 Nokia Corporation Instruction set processor enhancement for computing a fast fourier transform
US8631224B2 (en) * 2007-09-13 2014-01-14 Freescale Semiconductor, Inc. SIMD dot product operations with overlapped operands
US8478969B2 (en) * 2010-09-24 2013-07-02 Intel Corporation Performing a multiply-multiply-accumulate instruction
US10747501B2 (en) * 2017-08-31 2020-08-18 Qualcomm Incorporated Providing efficient floating-point operations using matrix processors in processor-based systems
EP3844608A4 (de) * 2018-08-31 2021-12-08 Flex Logix Technologies, Inc. Multiplikator-additionsschaltung, logische kachelarchitektur für multiplikation-addition und ic mit logischer kachelmatrix
US11093580B2 (en) * 2018-10-31 2021-08-17 Advanced Micro Devices, Inc. Matrix multiplier with submatrix sequencing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179531A (en) * 1990-04-27 1993-01-12 Pioneer Electronic Corporation Accelerated digital signal processor
EP0466997A1 (de) 1990-07-18 1992-01-22 International Business Machines Corporation Verbesserte digitale Signal-Verarbeitungsarchitektur
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
SG52303A1 (en) 1993-12-20 1998-09-28 Motorola Inc Arithmetic engine
KR0150350B1 (ko) * 1994-05-10 1998-10-15 모리시다 요이치 직교변환 프로세서
US5442580A (en) * 1994-05-25 1995-08-15 Tcsi Corporation Parallel processing circuit and a digital signal processer including same
US5801975A (en) * 1996-12-02 1998-09-01 Compaq Computer Corporation And Advanced Micro Devices, Inc. Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles
US5941940A (en) * 1997-06-30 1999-08-24 Lucent Technologies Inc. Digital signal processor architecture optimized for performing fast Fourier Transforms
US6530014B2 (en) * 1997-09-08 2003-03-04 Agere Systems Inc. Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits
US6029267A (en) * 1997-11-25 2000-02-22 Lucent Technologies Inc. Single-cycle, soft decision, compare-select operation using dual-add processor
US6526430B1 (en) * 1999-10-04 2003-02-25 Texas Instruments Incorporated Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
US6711602B1 (en) * 2000-02-18 2004-03-23 Texas Instruments Incorporated Data processor with flexible multiply unit

Also Published As

Publication number Publication date
EP1229438A2 (de) 2002-08-07
JP2002229970A (ja) 2002-08-16
US7043519B2 (en) 2006-05-09
EP1229438A3 (de) 2005-03-23
EP1229438B1 (de) 2010-11-17
JP3935678B2 (ja) 2007-06-27
US20020138535A1 (en) 2002-09-26

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Legal Events

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8328 Change in the person/name/address of the agent

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