DE60140674D1 - Verfahren und vorrichtung zum einfügen eines multiplizierers in ein nutzerprogrammierbares gatterfeld - Google Patents

Verfahren und vorrichtung zum einfügen eines multiplizierers in ein nutzerprogrammierbares gatterfeld

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Publication number
DE60140674D1
DE60140674D1 DE60140674T DE60140674T DE60140674D1 DE 60140674 D1 DE60140674 D1 DE 60140674D1 DE 60140674 T DE60140674 T DE 60140674T DE 60140674 T DE60140674 T DE 60140674T DE 60140674 D1 DE60140674 D1 DE 60140674D1
Authority
DE
Germany
Prior art keywords
multiplier
programmable gate
gate frame
user programmable
user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60140674T
Other languages
English (en)
Inventor
Bernard J New
Steven P Young
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60140674D1 publication Critical patent/DE60140674D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Complex Calculations (AREA)
DE60140674T 2000-05-18 2001-05-02 Verfahren und vorrichtung zum einfügen eines multiplizierers in ein nutzerprogrammierbares gatterfeld Expired - Lifetime DE60140674D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/574,714 US6362650B1 (en) 2000-05-18 2000-05-18 Method and apparatus for incorporating a multiplier into an FPGA
PCT/US2001/014259 WO2001089091A2 (en) 2000-05-18 2001-05-02 Method and apparatus for incorporating a multiplier into an fpga

Publications (1)

Publication Number Publication Date
DE60140674D1 true DE60140674D1 (de) 2010-01-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE60140674T Expired - Lifetime DE60140674D1 (de) 2000-05-18 2001-05-02 Verfahren und vorrichtung zum einfügen eines multiplizierers in ein nutzerprogrammierbares gatterfeld

Country Status (6)

Country Link
US (2) US6362650B1 (de)
EP (1) EP1303912B1 (de)
JP (1) JP4593866B2 (de)
CA (1) CA2409161C (de)
DE (1) DE60140674D1 (de)
WO (1) WO2001089091A2 (de)

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US6573749B2 (en) 2003-06-03
EP1303912B1 (de) 2009-12-02
CA2409161A1 (en) 2001-11-22
JP4593866B2 (ja) 2010-12-08
CA2409161C (en) 2010-07-13
US6362650B1 (en) 2002-03-26
WO2001089091A3 (en) 2002-09-26
JP2003533931A (ja) 2003-11-11
US20020057104A1 (en) 2002-05-16

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