DE60138106D1 - Architektur und verfahren zur teilrekonfiguration eines nutzerprogrammierbaren gatterfelds - Google Patents

Architektur und verfahren zur teilrekonfiguration eines nutzerprogrammierbaren gatterfelds

Info

Publication number
DE60138106D1
DE60138106D1 DE60138106T DE60138106T DE60138106D1 DE 60138106 D1 DE60138106 D1 DE 60138106D1 DE 60138106 T DE60138106 T DE 60138106T DE 60138106 T DE60138106 T DE 60138106T DE 60138106 D1 DE60138106 D1 DE 60138106D1
Authority
DE
Germany
Prior art keywords
architecture
programmable gate
particular configuration
gate field
user programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60138106T
Other languages
English (en)
Inventor
Steven P Young
Trevor J Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60138106D1 publication Critical patent/DE60138106D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE60138106T 2000-07-25 2001-07-16 Architektur und verfahren zur teilrekonfiguration eines nutzerprogrammierbaren gatterfelds Expired - Lifetime DE60138106D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/624,818 US6526557B1 (en) 2000-07-25 2000-07-25 Architecture and method for partially reconfiguring an FPGA
PCT/US2001/022120 WO2002009287A2 (en) 2000-07-25 2001-07-16 Architecture and method for partially reconfiguring an fpga

Publications (1)

Publication Number Publication Date
DE60138106D1 true DE60138106D1 (de) 2009-05-07

Family

ID=24503428

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60138106T Expired - Lifetime DE60138106D1 (de) 2000-07-25 2001-07-16 Architektur und verfahren zur teilrekonfiguration eines nutzerprogrammierbaren gatterfelds

Country Status (6)

Country Link
US (1) US6526557B1 (de)
EP (1) EP1303913B1 (de)
JP (1) JP4686107B2 (de)
CA (1) CA2415281C (de)
DE (1) DE60138106D1 (de)
WO (1) WO2002009287A2 (de)

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Also Published As

Publication number Publication date
CA2415281A1 (en) 2002-01-31
EP1303913A2 (de) 2003-04-23
EP1303913B1 (de) 2009-03-25
CA2415281C (en) 2010-09-28
JP2004505488A (ja) 2004-02-19
US6526557B1 (en) 2003-02-25
WO2002009287A3 (en) 2003-02-06
WO2002009287A2 (en) 2002-01-31
JP4686107B2 (ja) 2011-05-18

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