DE60137370D1 - Puffer mit reduzierten eingangs/ausgangspannungen - Google Patents

Puffer mit reduzierten eingangs/ausgangspannungen

Info

Publication number
DE60137370D1
DE60137370D1 DE60137370T DE60137370T DE60137370D1 DE 60137370 D1 DE60137370 D1 DE 60137370D1 DE 60137370 T DE60137370 T DE 60137370T DE 60137370 T DE60137370 T DE 60137370T DE 60137370 D1 DE60137370 D1 DE 60137370D1
Authority
DE
Germany
Prior art keywords
buffers
output voltages
reduced input
input
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60137370T
Other languages
English (en)
Inventor
Gerhard Mueller
David R Hanson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60137370D1 publication Critical patent/DE60137370D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
DE60137370T 2000-09-29 2001-09-19 Puffer mit reduzierten eingangs/ausgangspannungen Expired - Lifetime DE60137370D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/676,864 US6426658B1 (en) 2000-09-29 2000-09-29 Buffers with reduced voltage input/output signals
PCT/US2001/029192 WO2002029972A2 (en) 2000-09-29 2001-09-19 Buffers with reduced voltage input/output signals

Publications (1)

Publication Number Publication Date
DE60137370D1 true DE60137370D1 (de) 2009-02-26

Family

ID=24716342

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60137370T Expired - Lifetime DE60137370D1 (de) 2000-09-29 2001-09-19 Puffer mit reduzierten eingangs/ausgangspannungen

Country Status (4)

Country Link
US (1) US6426658B1 (de)
EP (1) EP1360765B1 (de)
DE (1) DE60137370D1 (de)
WO (1) WO2002029972A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040032284A1 (en) * 2002-06-13 2004-02-19 Stmicroelectronics Pvt. Ltd. Digital electronic circuit for translating high voltage levels to low voltage levels
TW589795B (en) * 2003-07-14 2004-06-01 Realtek Semiconductor Corp High-to-low level shift circuit
JP2005144707A (ja) * 2003-11-11 2005-06-09 Brother Ind Ltd 駆動回路及びインクジェットヘッド駆動回路
KR100541556B1 (ko) * 2004-03-29 2006-01-10 삼성전자주식회사 반도체 집적 회로 장치 및 이 장치의 온 다이 터미네이션회로
US8487695B2 (en) * 2011-09-23 2013-07-16 Tensorcom, Inc. Differential source follower having 6dB gain with applications to WiGig baseband filters
US9304534B1 (en) 2014-09-24 2016-04-05 Freescale Semiconductor, Inc. Low voltage swing buffer
KR20240028555A (ko) 2015-11-17 2024-03-05 텐서컴, 인코퍼레이티드 채널 선택 필터를 갖는 고 선형 WiGig 기저대역 증폭기

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109824A (ja) * 1987-10-22 1989-04-26 Nec Corp レベル変換回路
US5266848A (en) * 1990-03-28 1993-11-30 Hitachi, Ltd. CMOS circuit with reduced signal swing
JP2605565B2 (ja) * 1992-11-27 1997-04-30 日本電気株式会社 半導体集積回路
US5367205A (en) * 1993-05-13 1994-11-22 Micron Semiconductor, Inc. High speed output buffer with reduced voltage bounce and no cross current
JP3238826B2 (ja) * 1994-04-13 2001-12-17 富士通株式会社 出力回路
JP2964971B2 (ja) * 1997-01-24 1999-10-18 日本電気株式会社 プルアップ回路及びプルダウン回路
US5903142A (en) * 1997-06-27 1999-05-11 Cypress Semiconductor Corp. Low distortion level shifter
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit
US6191636B1 (en) * 1999-09-22 2001-02-20 Cypress Semiconductor Corp. Input buffer/level shifter

Also Published As

Publication number Publication date
EP1360765A2 (de) 2003-11-12
WO2002029972A2 (en) 2002-04-11
EP1360765B1 (de) 2009-01-07
WO2002029972A3 (en) 2003-07-10
US6426658B1 (en) 2002-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition