DE60129928D1 - Verfahren und Schaltung zur Zeitsteuerung des dynamischen Auslesens einer Speicherzelle mit Kontrolle der Integrationszeit - Google Patents

Verfahren und Schaltung zur Zeitsteuerung des dynamischen Auslesens einer Speicherzelle mit Kontrolle der Integrationszeit

Info

Publication number
DE60129928D1
DE60129928D1 DE60129928T DE60129928T DE60129928D1 DE 60129928 D1 DE60129928 D1 DE 60129928D1 DE 60129928 T DE60129928 T DE 60129928T DE 60129928 T DE60129928 T DE 60129928T DE 60129928 D1 DE60129928 D1 DE 60129928D1
Authority
DE
Germany
Prior art keywords
timing
circuit
memory cell
control
integration time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60129928T
Other languages
English (en)
Inventor
Rino Micheloni
Giovanni Campardo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60129928D1 publication Critical patent/DE60129928D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE60129928T 2001-04-19 2001-04-19 Verfahren und Schaltung zur Zeitsteuerung des dynamischen Auslesens einer Speicherzelle mit Kontrolle der Integrationszeit Expired - Lifetime DE60129928D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20010830266 EP1251523B1 (de) 2001-04-19 2001-04-19 Verfahren und Schaltung zur Zeitsteuerung des dynamischen Auslesens einer Speicherzelle mit Kontrolle der Integrationszeit

Publications (1)

Publication Number Publication Date
DE60129928D1 true DE60129928D1 (de) 2007-09-27

Family

ID=8184494

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60129928T Expired - Lifetime DE60129928D1 (de) 2001-04-19 2001-04-19 Verfahren und Schaltung zur Zeitsteuerung des dynamischen Auslesens einer Speicherzelle mit Kontrolle der Integrationszeit

Country Status (3)

Country Link
US (1) US6728141B2 (de)
EP (1) EP1251523B1 (de)
DE (1) DE60129928D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1729302B1 (de) * 2005-05-31 2019-01-02 Micron Technology, Inc. Schaltung zur Ermittlung von in Halbleiterspeicherzellen gespeicherten Daten.
US7742340B2 (en) * 2008-03-14 2010-06-22 Freescale Semiconductor, Inc. Read reference technique with current degradation protection
US7755946B2 (en) * 2008-09-19 2010-07-13 Sandisk Corporation Data state-based temperature compensation during sensing in non-volatile memory
US9633733B2 (en) * 2014-02-26 2017-04-25 Infineon Technologies Ag Method, apparatus and device for data processing for determining a predetermined state of a memory
US10084983B2 (en) * 2014-04-29 2018-09-25 Fermi Research Alliance, Llc Wafer-scale pixelated detector system
US11430531B2 (en) 2020-09-08 2022-08-30 Western Digital Technologies, Inc. Read integration time calibration for non-volatile storage

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687114A (en) * 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US5748534A (en) 1996-03-26 1998-05-05 Invox Technology Feedback loop for reading threshold voltage
US5726934A (en) 1996-04-09 1998-03-10 Information Storage Devices, Inc. Method and apparatus for analog reading values stored in floating gate structures
EP0833340B1 (de) 1996-09-30 2003-04-02 STMicroelectronics S.r.l. Leseschaltung für Halbleiter-Speicherzellen
US5914901A (en) * 1997-05-30 1999-06-22 Sgs-Thomson Microelectronics S.R.L. Integrated circuit for generating initialization signals for memory cell sensing circuits
KR100282707B1 (ko) * 1997-12-29 2001-02-15 윤종용 멀티-비트 데이터를 저장하는 반도체 메모리 장치 (semiconductor memory device for storing a multi-bit data)
ITTO980068A1 (it) 1998-01-27 1999-07-27 Sgs Thomson Microelectronics Circuito di lettura per memorie non volatili analogiche, in particola- re flash-eeprom, a lettura diretta della tensione di soglia e a corren
JP3600054B2 (ja) 1998-02-24 2004-12-08 三洋電機株式会社 不揮発性半導体メモリ装置
US5999454A (en) 1998-08-19 1999-12-07 Lucent Technologies, Inc. Sense amplifier for flash memory
US6337808B1 (en) 1999-08-30 2002-01-08 Micron Technology, Inc. Memory circuit and method of using same
US6188615B1 (en) * 1999-10-29 2001-02-13 Hewlett-Packard Company MRAM device including digital sense amplifiers
IT1318892B1 (it) * 2000-09-15 2003-09-19 St Microelectronics Srl Circuito di lettura per memorie non volatili a semiconduttore.
IT1319037B1 (it) 2000-10-27 2003-09-23 St Microelectronics Srl Circuito di lettura di memorie non volatili
US6724658B2 (en) * 2001-01-15 2004-04-20 Stmicroelectronics S.R.L. Method and circuit for generating reference voltages for reading a multilevel memory cell
DE60129786T2 (de) * 2001-01-15 2008-04-30 Stmicroelectronics S.R.L., Agrate Brianza Verfahren und Schaltung zum dynamischen Auslesen einer Speicherzelle, insbesondere einer nichtflüchtigen Multibitspeicherzelle
US6639833B2 (en) * 2001-02-14 2003-10-28 Stmicroelectronics S.R.L. Method and circuit for dynamic reading of a memory cell at low supply voltage and with low output dynamics

Also Published As

Publication number Publication date
US20020181277A1 (en) 2002-12-05
US6728141B2 (en) 2004-04-27
EP1251523B1 (de) 2007-08-15
EP1251523A1 (de) 2002-10-23

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Legal Events

Date Code Title Description
8332 No legal effect for de