DE60129605D1 - Ein verfahren zur herstellung von eingebetteten vertikal-dram-zellen und logikgates mit zweifacher arbeitsfunktion - Google Patents

Ein verfahren zur herstellung von eingebetteten vertikal-dram-zellen und logikgates mit zweifacher arbeitsfunktion

Info

Publication number
DE60129605D1
DE60129605D1 DE60129605T DE60129605T DE60129605D1 DE 60129605 D1 DE60129605 D1 DE 60129605D1 DE 60129605 T DE60129605 T DE 60129605T DE 60129605 T DE60129605 T DE 60129605T DE 60129605 D1 DE60129605 D1 DE 60129605D1
Authority
DE
Germany
Prior art keywords
logic gates
dram cells
working function
double working
embedded vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60129605T
Other languages
English (en)
Other versions
DE60129605T2 (de
Inventor
Ulrike Gruening
Ramachandra Divakaruni
Jack Mandelman
Thomas Rupp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Qimonda North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Publication of DE60129605D1 publication Critical patent/DE60129605D1/de
Application granted granted Critical
Publication of DE60129605T2 publication Critical patent/DE60129605T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
DE60129605T 2000-11-29 2001-11-28 Ein verfahren zur herstellung von eingebetteten vertikal-dram-zellen und logikgates mit zweifacher arbeitsfunktion Expired - Lifetime DE60129605T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US725412 2000-11-29
US09/725,412 US6258659B1 (en) 2000-11-29 2000-11-29 Embedded vertical DRAM cells and dual workfunction logic gates
PCT/US2001/044625 WO2002045130A2 (en) 2000-11-29 2001-11-28 Embedded vertical dram cells and dual workfunction logic gates

Publications (2)

Publication Number Publication Date
DE60129605D1 true DE60129605D1 (de) 2007-09-06
DE60129605T2 DE60129605T2 (de) 2008-06-05

Family

ID=24914450

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60129605T Expired - Lifetime DE60129605T2 (de) 2000-11-29 2001-11-28 Ein verfahren zur herstellung von eingebetteten vertikal-dram-zellen und logikgates mit zweifacher arbeitsfunktion

Country Status (7)

Country Link
US (1) US6258659B1 (de)
EP (1) EP1396010B1 (de)
KR (1) KR100392210B1 (de)
CN (1) CN100336203C (de)
DE (1) DE60129605T2 (de)
TW (1) TW512494B (de)
WO (1) WO2002045130A2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001319928A (ja) 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6509226B1 (en) * 2000-09-27 2003-01-21 International Business Machines Corporation Process for protecting array top oxide
US6610573B2 (en) * 2001-06-22 2003-08-26 Infineon Technologies Ag Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate
US6429068B1 (en) * 2001-07-02 2002-08-06 International Business Machines Corporation Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect
US6716734B2 (en) 2001-09-28 2004-04-06 Infineon Technologies Ag Low temperature sidewall oxidation of W/WN/poly-gatestack
US6709926B2 (en) * 2002-05-31 2004-03-23 International Business Machines Corporation High performance logic and high density embedded dram with borderless contact and antispacer
US6635526B1 (en) * 2002-06-07 2003-10-21 Infineon Technologies Ag Structure and method for dual work function logic devices in vertical DRAM process
US6750097B2 (en) 2002-07-30 2004-06-15 International Business Machines Corporation Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby
US6849495B2 (en) * 2003-02-28 2005-02-01 Infineon Technologies Ag Selective silicidation scheme for memory devices
US6972266B2 (en) * 2003-09-30 2005-12-06 International Business Machines Corporation Top oxide nitride liner integration scheme for vertical DRAM
US7018891B2 (en) * 2003-12-16 2006-03-28 International Business Machines Corporation Ultra-thin Si channel CMOS with improved series resistance
US9190494B2 (en) 2008-02-19 2015-11-17 Micron Technology, Inc. Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin
US7742324B2 (en) * 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US7915659B2 (en) 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
KR100960443B1 (ko) 2008-03-18 2010-05-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7808042B2 (en) 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
US8546876B2 (en) 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
US8148776B2 (en) 2008-09-15 2012-04-03 Micron Technology, Inc. Transistor with a passive gate
US8294511B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same
US8536656B2 (en) * 2011-01-10 2013-09-17 International Business Machines Corporation Self-aligned contacts for high k/metal gate process flow

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065273A (en) * 1990-12-04 1991-11-12 International Business Machines Corporation High capacity DRAM trench capacitor and methods of fabricating same
JP3150496B2 (ja) * 1993-06-30 2001-03-26 株式会社東芝 半導体記憶装置
US5827765A (en) 1996-02-22 1998-10-27 Siemens Aktiengesellschaft Buried-strap formation in a dram trench capacitor
JP2751909B2 (ja) * 1996-02-26 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5937296A (en) * 1996-12-20 1999-08-10 Siemens Aktiengesellschaft Memory cell that includes a vertical transistor and a trench capacitor
US5981332A (en) 1997-09-30 1999-11-09 Siemens Aktiengesellschaft Reduced parasitic leakage in semiconductor devices
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
US6153902A (en) * 1999-08-16 2000-11-28 International Business Machines Corporation Vertical DRAM cell with wordline self-aligned to storage trench
US6261894B1 (en) * 2000-11-03 2001-07-17 International Business Machines Corporation Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays

Also Published As

Publication number Publication date
CN1639860A (zh) 2005-07-13
KR100392210B1 (ko) 2003-07-23
WO2002045130A3 (en) 2004-01-08
EP1396010A2 (de) 2004-03-10
KR20020042420A (ko) 2002-06-05
CN100336203C (zh) 2007-09-05
DE60129605T2 (de) 2008-06-05
TW512494B (en) 2002-12-01
US6258659B1 (en) 2001-07-10
WO2002045130A2 (en) 2002-06-06
EP1396010B1 (de) 2007-07-25

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, A, US

Owner name: QIMONDA NORTH AMERICA CORP., CARY, N.C., US

8328 Change in the person/name/address of the agent

Representative=s name: EPPING HERMANN FISCHER, PATENTANWALTSGESELLSCHAFT

8364 No opposition during term of opposition