DE60121258D1 - Silizidverfahren mit einem variablen stöchiometrischen Verhältnis zwischen Silizium und Metall - Google Patents

Silizidverfahren mit einem variablen stöchiometrischen Verhältnis zwischen Silizium und Metall

Info

Publication number
DE60121258D1
DE60121258D1 DE60121258T DE60121258T DE60121258D1 DE 60121258 D1 DE60121258 D1 DE 60121258D1 DE 60121258 T DE60121258 T DE 60121258T DE 60121258 T DE60121258 T DE 60121258T DE 60121258 D1 DE60121258 D1 DE 60121258D1
Authority
DE
Germany
Prior art keywords
silicon
metal
stoichiometric ratio
silicide method
variable stoichiometric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60121258T
Other languages
English (en)
Inventor
Fuchao Wang
Ming Fang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60121258D1 publication Critical patent/DE60121258D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE60121258T 2000-06-15 2001-05-18 Silizidverfahren mit einem variablen stöchiometrischen Verhältnis zwischen Silizium und Metall Expired - Lifetime DE60121258D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/594,868 US6350684B1 (en) 2000-06-15 2000-06-15 Graded/stepped silicide process to improve MOS transistor

Publications (1)

Publication Number Publication Date
DE60121258D1 true DE60121258D1 (de) 2006-08-17

Family

ID=24380751

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60121258T Expired - Lifetime DE60121258D1 (de) 2000-06-15 2001-05-18 Silizidverfahren mit einem variablen stöchiometrischen Verhältnis zwischen Silizium und Metall

Country Status (4)

Country Link
US (2) US6350684B1 (de)
EP (1) EP1164630B1 (de)
JP (1) JP2002033294A (de)
DE (1) DE60121258D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019643A1 (fr) * 2001-08-23 2003-03-06 Nec Corporation Dispositif semi-conducteur comportant un film isolant presentant une permittivite elevee et son procede de production
KR100871006B1 (ko) * 2004-07-30 2008-11-27 어플라이드 머티어리얼스, 인코포레이티드 얇은 텅스텐 실리사이드층 증착 및 게이트 금속 집적화
KR100650858B1 (ko) * 2005-12-23 2006-11-28 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법
US8741773B2 (en) 2010-01-08 2014-06-03 International Business Machines Corporation Nickel-silicide formation with differential Pt composition
US10903330B2 (en) * 2013-11-27 2021-01-26 General Electric Company Tapered gate electrode for semiconductor devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4954852A (en) * 1987-12-24 1990-09-04 Ford Microelectronics, Inc. Sputtered metallic silicide gate for GaAs integrated circuits
EP0785574A3 (de) * 1996-01-16 1998-07-29 Applied Materials, Inc. Herstellungsverfahren von Wolfram-Silizid
US5654219A (en) * 1996-02-07 1997-08-05 Texas Instruments Incorporated Annealed poly-silicide etch process
US5635765A (en) 1996-02-26 1997-06-03 Cypress Semiconductor Corporation Multi-layer gate structure
US5725739A (en) * 1996-07-08 1998-03-10 Micron Technology, Inc. Low angle, low energy physical vapor deposition of alloys
US6087254A (en) * 1996-07-16 2000-07-11 Micron Technology, Inc. Technique for elimination of pitting on silicon substrate during gate stack etch
US6153452A (en) * 1997-01-07 2000-11-28 Lucent Technologies Inc. Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure
KR100243291B1 (ko) * 1997-04-30 2000-03-02 윤종용 반도체장치의제조공정에서실리사이드층형성방법
JPH11200050A (ja) * 1998-01-14 1999-07-27 Mitsubishi Electric Corp タングステンシリサイド膜の形成方法、半導体装置の製造方法、及び半導体ウェーハ処理装置
US6103607A (en) * 1998-09-15 2000-08-15 Lucent Technologies Manufacture of MOSFET devices
US6331460B1 (en) * 1999-11-17 2001-12-18 Agere Systems Guardian Corp. Method of fabricating a mom capacitor having a metal silicide barrier

Also Published As

Publication number Publication date
EP1164630A3 (de) 2002-12-18
US6350684B1 (en) 2002-02-26
US7465660B2 (en) 2008-12-16
EP1164630B1 (de) 2006-07-05
EP1164630A2 (de) 2001-12-19
US20030211733A1 (en) 2003-11-13
JP2002033294A (ja) 2002-01-31

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Legal Events

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