DE60044311D1 - Programmierbare logische Vorrichtung mit vereinheitlichter Zellstruktur und mit Signalverbindungsschwellen - Google Patents

Programmierbare logische Vorrichtung mit vereinheitlichter Zellstruktur und mit Signalverbindungsschwellen

Info

Publication number
DE60044311D1
DE60044311D1 DE60044311T DE60044311T DE60044311D1 DE 60044311 D1 DE60044311 D1 DE 60044311D1 DE 60044311 T DE60044311 T DE 60044311T DE 60044311 T DE60044311 T DE 60044311T DE 60044311 D1 DE60044311 D1 DE 60044311D1
Authority
DE
Germany
Prior art keywords
programmable logic
logic device
cell structure
signal connection
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60044311T
Other languages
English (en)
Inventor
Sergey Shumarayev
Wei-Jen Huang
Rakesh Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of DE60044311D1 publication Critical patent/DE60044311D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE60044311T 1999-07-15 2000-07-14 Programmierbare logische Vorrichtung mit vereinheitlichter Zellstruktur und mit Signalverbindungsschwellen Expired - Lifetime DE60044311D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14397699P 1999-07-15 1999-07-15

Publications (1)

Publication Number Publication Date
DE60044311D1 true DE60044311D1 (de) 2010-06-10

Family

ID=22506525

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60044311T Expired - Lifetime DE60044311D1 (de) 1999-07-15 2000-07-14 Programmierbare logische Vorrichtung mit vereinheitlichter Zellstruktur und mit Signalverbindungsschwellen

Country Status (5)

Country Link
US (1) US6351144B1 (de)
EP (2) EP1069686A3 (de)
JP (1) JP2001135728A (de)
AT (1) ATE466409T1 (de)
DE (1) DE60044311D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8124429B2 (en) * 2006-12-15 2012-02-28 Richard Norman Reprogrammable circuit board with alignment-insensitive support for multiple component contact types
JP2015039155A (ja) * 2013-08-19 2015-02-26 富士通株式会社 制御方法、演算装置、および制御プログラム
CN109086467B (zh) * 2017-06-14 2023-05-02 上海复旦微电子集团股份有限公司 可编程逻辑器件的i/o单元布局方法及装置、介质及设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
JPH09503622A (ja) * 1993-09-30 1997-04-08 コピン・コーポレーシヨン 転写薄膜回路を使用した３次元プロセッサー
US5512765A (en) * 1994-02-03 1996-04-30 National Semiconductor Corporation Extendable circuit architecture
EP0698294A1 (de) * 1994-03-15 1996-02-28 National Semiconductor Corporation Dreidimensionale logische verbindungen zwischen integrierten schaltungschips mit zweidimensionaler multichip-modulverpackung
US5642262A (en) * 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5838060A (en) * 1995-12-12 1998-11-17 Comer; Alan E. Stacked assemblies of semiconductor packages containing programmable interconnect
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits

Also Published As

Publication number Publication date
EP1667325B1 (de) 2010-04-28
US6351144B1 (en) 2002-02-26
EP1667325A1 (de) 2006-06-07
EP1069686A2 (de) 2001-01-17
JP2001135728A (ja) 2001-05-18
ATE466409T1 (de) 2010-05-15
EP1069686A3 (de) 2003-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition