ATE466409T1 - Programmierbare logische vorrichtung mit vereinheitlichter zellstruktur und mit signalverbindungsschwellen - Google Patents

Programmierbare logische vorrichtung mit vereinheitlichter zellstruktur und mit signalverbindungsschwellen

Info

Publication number
ATE466409T1
ATE466409T1 AT06000671T AT06000671T ATE466409T1 AT E466409 T1 ATE466409 T1 AT E466409T1 AT 06000671 T AT06000671 T AT 06000671T AT 06000671 T AT06000671 T AT 06000671T AT E466409 T1 ATE466409 T1 AT E466409T1
Authority
AT
Austria
Prior art keywords
cell structure
signal connection
logical device
programmable logical
package
Prior art date
Application number
AT06000671T
Other languages
English (en)
Inventor
Sergey Shumarayev
Wei-Jen Huang
Rakesh Patel
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of ATE466409T1 publication Critical patent/ATE466409T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
AT06000671T 1999-07-15 2000-07-14 Programmierbare logische vorrichtung mit vereinheitlichter zellstruktur und mit signalverbindungsschwellen ATE466409T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14397699P 1999-07-15 1999-07-15

Publications (1)

Publication Number Publication Date
ATE466409T1 true ATE466409T1 (de) 2010-05-15

Family

ID=22506525

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06000671T ATE466409T1 (de) 1999-07-15 2000-07-14 Programmierbare logische vorrichtung mit vereinheitlichter zellstruktur und mit signalverbindungsschwellen

Country Status (5)

Country Link
US (1) US6351144B1 (de)
EP (2) EP1667325B1 (de)
JP (1) JP2001135728A (de)
AT (1) ATE466409T1 (de)
DE (1) DE60044311D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8124429B2 (en) * 2006-12-15 2012-02-28 Richard Norman Reprogrammable circuit board with alignment-insensitive support for multiple component contact types
JP2015039155A (ja) * 2013-08-19 2015-02-26 富士通株式会社 制御方法、演算装置、および制御プログラム
CN109086467B (zh) * 2017-06-14 2023-05-02 上海复旦微电子集团股份有限公司 可编程逻辑器件的i/o单元布局方法及装置、介质及设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8918482D0 (en) * 1989-08-14 1989-09-20 Inmos Ltd Packaging semiconductor chips
JPH09503622A (ja) * 1993-09-30 1997-04-08 コピン・コーポレーシヨン 転写薄膜回路を使用した３次元プロセッサー
US5512765A (en) * 1994-02-03 1996-04-30 National Semiconductor Corporation Extendable circuit architecture
WO1995025348A1 (en) * 1994-03-15 1995-09-21 National Semiconductor Corporation Logical three-dimensional interconnections between integrated circuit chips using a two-dimensional multi-chip module package
US5642262A (en) * 1995-02-23 1997-06-24 Altera Corporation High-density programmable logic device in a multi-chip module package with improved interconnect scheme
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips
US5838060A (en) * 1995-12-12 1998-11-17 Comer; Alan E. Stacked assemblies of semiconductor packages containing programmable interconnect
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits

Also Published As

Publication number Publication date
DE60044311D1 (de) 2010-06-10
EP1069686A2 (de) 2001-01-17
EP1667325A1 (de) 2006-06-07
EP1069686A3 (de) 2003-01-02
EP1667325B1 (de) 2010-04-28
JP2001135728A (ja) 2001-05-18
US6351144B1 (en) 2002-02-26

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Legal Events

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