DE60005219T2 - Aufbauen eines betriebsmodus in einem prozessor - Google Patents

Aufbauen eines betriebsmodus in einem prozessor Download PDF

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Publication number
DE60005219T2
DE60005219T2 DE60005219T DE60005219T DE60005219T2 DE 60005219 T2 DE60005219 T2 DE 60005219T2 DE 60005219 T DE60005219 T DE 60005219T DE 60005219 T DE60005219 T DE 60005219T DE 60005219 T2 DE60005219 T2 DE 60005219T2
Authority
DE
Germany
Prior art keywords
processor
operating mode
bit
mode
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60005219T
Other languages
German (de)
English (en)
Other versions
DE60005219D1 (de
Inventor
J. Kevin MCGRATH
T. Michael CLARK
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60005219D1 publication Critical patent/DE60005219D1/de
Publication of DE60005219T2 publication Critical patent/DE60005219T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60005219T 2000-01-14 2000-07-19 Aufbauen eines betriebsmodus in einem prozessor Expired - Lifetime DE60005219T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US483101 2000-01-14
US09/483,101 US6973562B1 (en) 2000-01-14 2000-01-14 Establishing an operating mode in a processor
PCT/US2000/019762 WO2001052058A1 (en) 2000-01-14 2000-07-19 Establishing an operating mode in a processor

Publications (2)

Publication Number Publication Date
DE60005219D1 DE60005219D1 (de) 2003-10-16
DE60005219T2 true DE60005219T2 (de) 2004-06-24

Family

ID=23918664

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60005219T Expired - Lifetime DE60005219T2 (de) 2000-01-14 2000-07-19 Aufbauen eines betriebsmodus in einem prozessor

Country Status (8)

Country Link
US (1) US6973562B1 (https=)
EP (1) EP1247171B1 (https=)
JP (1) JP4520683B2 (https=)
KR (1) KR100636413B1 (https=)
CN (1) CN100419671C (https=)
DE (1) DE60005219T2 (https=)
TW (1) TW567434B (https=)
WO (1) WO2001052058A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387250B8 (en) * 2002-07-31 2012-02-29 Texas Instruments Inc. Processor that accomodates multiple instruction sets and multiple decode modes
US7343378B2 (en) * 2004-03-29 2008-03-11 Microsoft Corporation Generation of meaningful names in flattened hierarchical structures
US7437541B2 (en) * 2004-07-08 2008-10-14 International Business Machiens Corporation Atomically updating 64 bit fields in the 32 bit AIX kernel
US20060282606A1 (en) * 2005-06-08 2006-12-14 Dell Products L.P. System and method for automatically optimizing available virtual memory
JP5289688B2 (ja) * 2006-07-05 2013-09-11 ルネサスエレクトロニクス株式会社 プロセッサシステム及びプロセッサシステムを動作させるオペレーティングシステムプログラムの処理方法
US7451298B2 (en) * 2006-08-03 2008-11-11 Apple Inc. Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode
US7802252B2 (en) * 2007-01-09 2010-09-21 International Business Machines Corporation Method and apparatus for selecting the architecture level to which a processor appears to conform
US8938606B2 (en) * 2010-12-22 2015-01-20 Intel Corporation System, apparatus, and method for segment register read and write regardless of privilege level
US8528083B2 (en) * 2011-03-10 2013-09-03 Adobe Systems Incorporated Using a call gate to prevent secure sandbox leakage
US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
CN102331978A (zh) * 2011-07-07 2012-01-25 曙光信息产业股份有限公司 一种龙芯刀片大内存地址设备dma控制器访问的实现方法
CN105094870A (zh) * 2014-05-13 2015-11-25 中标软件有限公司 64位Linux操作系统兼容32位应用软件的方法
GB2522290B (en) * 2014-07-14 2015-12-09 Imagination Tech Ltd Running a 32-bit operating system on a 64-bit machine
GB2546465B (en) * 2015-06-05 2018-02-28 Advanced Risc Mach Ltd Modal processing of program instructions
CN107870736B (zh) * 2016-09-28 2021-08-10 龙芯中科技术股份有限公司 支持大于4gb非线性闪存的方法及装置
CN111026452B (zh) * 2019-11-20 2023-10-20 北京明朝万达科技股份有限公司 一种远程32位进程注入64位进程的方法及系统

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620274A (en) 1983-04-01 1986-10-28 Honeywell Information Systems Inc. Data available indicator for an exhausted operand string
US4701946A (en) 1984-10-23 1987-10-20 Oliva Raymond A Device for controlling the application of power to a computer
US4868740A (en) 1986-06-04 1989-09-19 Hitachi, Ltd. System for processing data with multiple virtual address and data word lengths
JPS63174145A (ja) * 1987-01-14 1988-07-18 Hitachi Ltd デ−タ処理装置
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
US5381537A (en) * 1991-12-06 1995-01-10 International Business Machines Corporation Large logical addressing method and means
US5617554A (en) * 1992-02-10 1997-04-01 Intel Corporation Physical address size selection and page size selection in an address translator
US5692167A (en) * 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5517651A (en) 1993-12-29 1996-05-14 Intel Corporation Method and apparatus for loading a segment register in a microprocessor capable of operating in multiple modes
US5481684A (en) * 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5758116A (en) 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5644755A (en) 1995-02-24 1997-07-01 Compaq Computer Corporation Processor with virtual system mode
US5774686A (en) * 1995-06-07 1998-06-30 Intel Corporation Method and apparatus for providing two system architectures in a processor
US5787495A (en) 1995-12-18 1998-07-28 Integrated Device Technology, Inc. Method and apparatus for selector storing and restoration
US5784638A (en) 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US5826074A (en) 1996-11-22 1998-10-20 S3 Incorporated Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
US6086623A (en) 1997-06-30 2000-07-11 Sun Microsystems, Inc. Method and implementation for intercepting and processing system calls in programmed digital computer to emulate retrograde operating system

Also Published As

Publication number Publication date
KR20020091066A (ko) 2002-12-05
KR100636413B1 (ko) 2006-10-19
US6973562B1 (en) 2005-12-06
TW567434B (en) 2003-12-21
JP4520683B2 (ja) 2010-08-11
EP1247171B1 (en) 2003-09-10
WO2001052058A1 (en) 2001-07-19
EP1247171A1 (en) 2002-10-09
DE60005219D1 (de) 2003-10-16
CN100419671C (zh) 2008-09-17
CN1423773A (zh) 2003-06-11
JP2003519868A (ja) 2003-06-24

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