DE60001923T2 - Schaltung zur Erzeugung eines logischen Ausgangssignals ,das mit Kreuzpunkten von differentiellen Signalen korrespondiert - Google Patents

Schaltung zur Erzeugung eines logischen Ausgangssignals ,das mit Kreuzpunkten von differentiellen Signalen korrespondiert Download PDF

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Publication number
DE60001923T2
DE60001923T2 DE60001923T DE60001923T DE60001923T2 DE 60001923 T2 DE60001923 T2 DE 60001923T2 DE 60001923 T DE60001923 T DE 60001923T DE 60001923 T DE60001923 T DE 60001923T DE 60001923 T2 DE60001923 T2 DE 60001923T2
Authority
DE
Germany
Prior art keywords
generating
circuit
output signal
signal corresponding
differential signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60001923T
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English (en)
Other versions
DE60001923D1 (de
Inventor
Bernhard Roth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE60001923D1 publication Critical patent/DE60001923D1/de
Application granted granted Critical
Publication of DE60001923T2 publication Critical patent/DE60001923T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2409—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors
    • H03K5/2418—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using bipolar transistors with at least one differential stage

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)
DE60001923T 2000-11-24 2000-11-24 Schaltung zur Erzeugung eines logischen Ausgangssignals ,das mit Kreuzpunkten von differentiellen Signalen korrespondiert Expired - Lifetime DE60001923T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00125758A EP1152530B1 (de) 2000-11-24 2000-11-24 Schaltung zur Erzeugung eines logischen Ausgangssignals ,das mit Kreuzpunkten von differentiellen Signalen korrespondiert

Publications (2)

Publication Number Publication Date
DE60001923D1 DE60001923D1 (de) 2003-05-08
DE60001923T2 true DE60001923T2 (de) 2004-01-15

Family

ID=8170471

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60001923T Expired - Lifetime DE60001923T2 (de) 2000-11-24 2000-11-24 Schaltung zur Erzeugung eines logischen Ausgangssignals ,das mit Kreuzpunkten von differentiellen Signalen korrespondiert

Country Status (4)

Country Link
US (1) US6448806B1 (de)
EP (1) EP1152530B1 (de)
JP (1) JP3935338B2 (de)
DE (1) DE60001923T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703866B1 (en) * 2000-12-19 2004-03-09 International Business Machines Corporation Selectable interface for interfacing integrated circuit modules
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7151367B2 (en) * 2004-03-31 2006-12-19 Teradyne, Inc. Method of measuring duty cycle
WO2006019007A1 (ja) * 2004-08-16 2006-02-23 Advantest Corporation 差動コンパレータ回路、テストヘッド、及び試験装置
US7294993B2 (en) * 2004-08-25 2007-11-13 International Rectifier Corporation Method and apparatus for customizing of a power supply based on load characteristic data
US7734866B2 (en) * 2005-08-04 2010-06-08 Rambus Inc. Memory with address-differentiated refresh rate to accommodate low-retention storage rows
US7524077B2 (en) * 2006-09-07 2009-04-28 Hartman Michael S Lamp and illuminated hardscape
US7808282B2 (en) * 2008-11-25 2010-10-05 Pericom Semiconductor Corp. Out-of-band signaling using detector with equalizer, multiplier and comparator
US7786762B2 (en) * 2009-01-21 2010-08-31 Xilinx, Inc. Generic buffer circuits and methods for out of band signaling
US8476934B2 (en) 2011-07-21 2013-07-02 National Semiconductor Corporation Circuitry and method for differential signal detection with integrated reference voltage
US8933729B1 (en) * 2012-03-30 2015-01-13 Rambus Inc. Stacked receivers
CN105652070B (zh) * 2016-01-21 2018-11-30 烽火通信科技股份有限公司 一种差分信号幅度检测电路
KR102409877B1 (ko) * 2017-12-21 2022-06-20 에스케이하이닉스 주식회사 수신 회로 및 이를 이용하는 집적 회로 시스템
US11271566B2 (en) * 2018-12-14 2022-03-08 Integrated Device Technology, Inc. Digital logic compatible inputs in compound semiconductor circuits

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3331109B2 (ja) * 1996-01-23 2002-10-07 株式会社アドバンテスト 半導体試験装置の比較器
US6377073B1 (en) * 1999-11-30 2002-04-23 Texas Instruments Incorporated Structure and method for reduction of power consumption in integrated circuit logic
US6281699B1 (en) * 2000-03-15 2001-08-28 Teradyne, Inc. Detector with common mode comparator for automatic test equipment

Also Published As

Publication number Publication date
JP3935338B2 (ja) 2007-06-20
JP2002208843A (ja) 2002-07-26
EP1152530B1 (de) 2003-04-02
DE60001923D1 (de) 2003-05-08
US6448806B1 (en) 2002-09-10
EP1152530A1 (de) 2001-11-07
US20020075035A1 (en) 2002-06-20

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8327 Change in the person/name/address of the patent owner

Owner name: VERIGY (SINGAPORE) PTE. LTD., SINGAPORE, SG

R082 Change of representative

Ref document number: 1152530

Country of ref document: EP

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER, ZINKLER & PARTNER