DE50013674D1 - CMOS kompatibler SOI-Prozess - Google Patents
CMOS kompatibler SOI-ProzessInfo
- Publication number
- DE50013674D1 DE50013674D1 DE50013674T DE50013674T DE50013674D1 DE 50013674 D1 DE50013674 D1 DE 50013674D1 DE 50013674 T DE50013674 T DE 50013674T DE 50013674 T DE50013674 T DE 50013674T DE 50013674 D1 DE50013674 D1 DE 50013674D1
- Authority
- DE
- Germany
- Prior art keywords
- troughs
- components
- type
- trough
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
- Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
- Thin Film Transistor (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE50013674T DE50013674D1 (de) | 1999-07-06 | 2000-07-05 | CMOS kompatibler SOI-Prozess |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19931030 | 1999-07-06 | ||
EP99121430 | 1999-10-27 | ||
DE50013674T DE50013674D1 (de) | 1999-07-06 | 2000-07-05 | CMOS kompatibler SOI-Prozess |
Publications (1)
Publication Number | Publication Date |
---|---|
DE50013674D1 true DE50013674D1 (de) | 2006-12-14 |
Family
ID=26054057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE50013674T Expired - Lifetime DE50013674D1 (de) | 1999-07-06 | 2000-07-05 | CMOS kompatibler SOI-Prozess |
Country Status (3)
Country | Link |
---|---|
US (1) | US6326288B1 (de) |
AT (1) | ATE344535T1 (de) |
DE (1) | DE50013674D1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6573565B2 (en) * | 1999-07-28 | 2003-06-03 | International Business Machines Corporation | Method and structure for providing improved thermal conduction for silicon semiconductor devices |
CN1757123A (zh) | 2003-01-14 | 2006-04-05 | 波尔伊克两合公司 | 有机场效应晶体管和集成电路 |
JP4065855B2 (ja) * | 2004-01-21 | 2008-03-26 | 株式会社日立製作所 | 生体および化学試料検査装置 |
DE102005017655B4 (de) | 2005-04-15 | 2008-12-11 | Polyic Gmbh & Co. Kg | Mehrschichtiger Verbundkörper mit elektronischer Funktion |
DE102005031448A1 (de) | 2005-07-04 | 2007-01-11 | Polyic Gmbh & Co. Kg | Aktivierbare optische Schicht |
DE102005035589A1 (de) | 2005-07-29 | 2007-02-01 | Polyic Gmbh & Co. Kg | Verfahren zur Herstellung eines elektronischen Bauelements |
DE102005044306A1 (de) | 2005-09-16 | 2007-03-22 | Polyic Gmbh & Co. Kg | Elektronische Schaltung und Verfahren zur Herstellung einer solchen |
DE102006047388A1 (de) * | 2006-10-06 | 2008-04-17 | Polyic Gmbh & Co. Kg | Feldeffekttransistor sowie elektrische Schaltung |
EP1998372A1 (de) * | 2007-05-30 | 2008-12-03 | NEC Electronics Corporation | SOI Halbleiterbauelement |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4578128A (en) * | 1984-12-03 | 1986-03-25 | Ncr Corporation | Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants |
US4740827A (en) * | 1985-09-30 | 1988-04-26 | Kabushiki Kaisha Toshiba | CMOS semiconductor device |
US5053350A (en) * | 1989-03-23 | 1991-10-01 | Grumman Aerospace Corporation | Method of making trench MOSFET capacitor cell for analog signal processing |
JP3097200B2 (ja) * | 1991-08-26 | 2000-10-10 | 日本電気株式会社 | 半導体装置 |
US5382541A (en) * | 1992-08-26 | 1995-01-17 | Harris Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
JP3273582B2 (ja) * | 1994-05-13 | 2002-04-08 | キヤノン株式会社 | 記憶装置 |
US5583368A (en) * | 1994-08-11 | 1996-12-10 | International Business Machines Corporation | Stacked devices |
US5622880A (en) * | 1994-08-18 | 1997-04-22 | Sun Microsystems, Inc. | Method of making a low power, high performance junction transistor |
US5559368A (en) * | 1994-08-30 | 1996-09-24 | The Regents Of The University Of California | Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation |
JPH08153804A (ja) * | 1994-09-28 | 1996-06-11 | Sony Corp | ゲート電極の形成方法 |
US6172405B1 (en) * | 1998-07-17 | 2001-01-09 | Sharp Kabushiki Kaisha | Semiconductor device and production process therefore |
-
2000
- 2000-07-05 DE DE50013674T patent/DE50013674D1/de not_active Expired - Lifetime
- 2000-07-05 AT AT00114377T patent/ATE344535T1/de active
- 2000-07-06 US US09/610,886 patent/US6326288B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6326288B1 (en) | 2001-12-04 |
ATE344535T1 (de) | 2006-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |