DE3882248T2 - Vorrichtung zur Ermöglichung des Zugriffes zweier Signalverarbeitungsprozessoren auf eine gemeinsame Schaltung. - Google Patents

Vorrichtung zur Ermöglichung des Zugriffes zweier Signalverarbeitungsprozessoren auf eine gemeinsame Schaltung.

Info

Publication number
DE3882248T2
DE3882248T2 DE88200302T DE3882248T DE3882248T2 DE 3882248 T2 DE3882248 T2 DE 3882248T2 DE 88200302 T DE88200302 T DE 88200302T DE 3882248 T DE3882248 T DE 3882248T DE 3882248 T2 DE3882248 T2 DE 3882248T2
Authority
DE
Germany
Prior art keywords
enabling
access
signal processing
common circuit
processing processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88200302T
Other languages
English (en)
Other versions
DE3882248D1 (de
Inventor
Andre Societe Civi Bussonniere
Yves Societe Civile S Courtois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3882248D1 publication Critical patent/DE3882248D1/de
Application granted granted Critical
Publication of DE3882248T2 publication Critical patent/DE3882248T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
  • Hardware Redundancy (AREA)
DE88200302T 1987-02-27 1988-02-19 Vorrichtung zur Ermöglichung des Zugriffes zweier Signalverarbeitungsprozessoren auf eine gemeinsame Schaltung. Expired - Fee Related DE3882248T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8702659A FR2611396B1 (fr) 1987-02-27 1987-02-27 Dispositif pour permettre a deux systemes de traitement d'informations l'acces a un circuit commun

Publications (2)

Publication Number Publication Date
DE3882248D1 DE3882248D1 (de) 1993-08-19
DE3882248T2 true DE3882248T2 (de) 1994-02-03

Family

ID=9348419

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88200302T Expired - Fee Related DE3882248T2 (de) 1987-02-27 1988-02-19 Vorrichtung zur Ermöglichung des Zugriffes zweier Signalverarbeitungsprozessoren auf eine gemeinsame Schaltung.

Country Status (5)

Country Link
US (1) US4872108A (de)
EP (1) EP0280369B1 (de)
JP (1) JPS63228366A (de)
DE (1) DE3882248T2 (de)
FR (1) FR2611396B1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2749819B2 (ja) * 1987-10-26 1998-05-13 松下電工株式会社 共有メモリ制御方式
JPH01282668A (ja) * 1988-05-10 1989-11-14 Sharp Corp 処理時間調停方式

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking
JPS53146550A (en) * 1977-05-27 1978-12-20 Nippon Telegr & Teleph Corp <Ntt> Conflict circuit
US4282572A (en) * 1979-01-15 1981-08-04 Ncr Corporation Multiprocessor memory access system
JPS564854A (en) * 1979-06-22 1981-01-19 Fanuc Ltd Control system for plural microprocessors
US4325116A (en) * 1979-08-21 1982-04-13 International Business Machines Corporation Parallel storage access by multiprocessors
US4594657A (en) * 1983-04-22 1986-06-10 Motorola, Inc. Semaphore for memory shared by two asynchronous microcomputers
JPS59220821A (ja) * 1983-05-31 1984-12-12 Nec Home Electronics Ltd コンピユ−タの共有バス制御装置
JPS6091473A (ja) * 1983-10-25 1985-05-22 Oki Electric Ind Co Ltd メモリマルチアクセス方式
JPS60246470A (ja) * 1984-05-21 1985-12-06 Anritsu Corp コンピユ−タシステム
DE3502721A1 (de) * 1985-01-28 1986-07-31 Robert Bosch Gmbh, 7000 Stuttgart Multiprozessorsystem

Also Published As

Publication number Publication date
EP0280369B1 (de) 1993-07-14
US4872108A (en) 1989-10-03
DE3882248D1 (de) 1993-08-19
FR2611396A1 (fr) 1988-09-02
FR2611396B1 (fr) 1991-10-11
JPS63228366A (ja) 1988-09-22
EP0280369A1 (de) 1988-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee