DE3880019D1 - Oberflaechenabschluss eines verbindungshalbleiters. - Google Patents

Oberflaechenabschluss eines verbindungshalbleiters.

Info

Publication number
DE3880019D1
DE3880019D1 DE8888108684T DE3880019T DE3880019D1 DE 3880019 D1 DE3880019 D1 DE 3880019D1 DE 8888108684 T DE8888108684 T DE 8888108684T DE 3880019 T DE3880019 T DE 3880019T DE 3880019 D1 DE3880019 D1 DE 3880019D1
Authority
DE
Germany
Prior art keywords
surface termination
connection semiconductor
semiconductor
connection
termination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888108684T
Other languages
English (en)
Other versions
DE3880019T2 (de
Inventor
Alan B Fowler
John L Freeouf
Peter D Kirchner
Alan C Warren
Jerry M Woodall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3880019D1 publication Critical patent/DE3880019D1/de
Publication of DE3880019T2 publication Critical patent/DE3880019T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
DE88108684T 1987-06-18 1988-05-31 Oberflächenabschluss eines Verbindungshalbleiters. Expired - Fee Related DE3880019T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/064,414 US4811077A (en) 1987-06-18 1987-06-18 Compound semiconductor surface termination

Publications (2)

Publication Number Publication Date
DE3880019D1 true DE3880019D1 (de) 1993-05-13
DE3880019T2 DE3880019T2 (de) 1993-10-28

Family

ID=22055822

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88108684T Expired - Fee Related DE3880019T2 (de) 1987-06-18 1988-05-31 Oberflächenabschluss eines Verbindungshalbleiters.

Country Status (4)

Country Link
US (1) US4811077A (de)
EP (1) EP0295490B1 (de)
JP (1) JPH079914B2 (de)
DE (1) DE3880019T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920009718B1 (ko) * 1987-08-10 1992-10-22 스미도모덴기고오교오 가부시기가이샤 화합물반도체장치 및 그 제조방법
US5086321A (en) * 1988-06-15 1992-02-04 International Business Machines Corporation Unpinned oxide-compound semiconductor structures and method of forming same
JP2586626B2 (ja) * 1989-01-20 1997-03-05 日本電気株式会社 エピタキシャル成長方法
US5122424A (en) * 1989-10-05 1992-06-16 Litton Systems, Inc. Abrasion-resistant, infrared transmitting optical components
JPH03261147A (ja) * 1990-03-12 1991-11-21 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法並びにその製造装置
JPH04199518A (ja) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp 電界効果トランジスタ及びその製造方法
AU4695096A (en) * 1995-01-06 1996-07-24 National Aeronautics And Space Administration - Nasa Minority carrier device
US5760462A (en) * 1995-01-06 1998-06-02 President And Fellows Of Harvard College Metal, passivating layer, semiconductor, field-effect transistor
WO1997048499A1 (en) * 1996-06-19 1997-12-24 The Board Of Trustees Of Southern Illinois University GaAs SUBSTRATE WITH A PASSIVATING EPITAXIAL GALLIUM SULFIDE FILM AND METHODS FOR FORMING SAME
US5799028A (en) * 1996-07-18 1998-08-25 Sdl, Inc. Passivation and protection of a semiconductor surface
US6304583B1 (en) 1999-07-26 2001-10-16 The United States Of America As Represented By The Secretary Of The Air Force Utilization of telluride quaternary nonlinear optic materials
US6508960B1 (en) 1999-07-26 2003-01-21 The United States Of America As Represented By The Secretary Of The Air Force Telluride quaternary nonlinear optic materials
US7176483B2 (en) * 2002-08-12 2007-02-13 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US7902029B2 (en) 2002-08-12 2011-03-08 Acorn Technologies, Inc. Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
US6833556B2 (en) * 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US6791125B2 (en) * 2002-09-30 2004-09-14 Freescale Semiconductor, Inc. Semiconductor device structures which utilize metal sulfides
US6770536B2 (en) * 2002-10-03 2004-08-03 Agere Systems Inc. Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate
JP4880359B2 (ja) * 2006-05-23 2012-02-22 Ｎｅｃディスプレイソリューションズ株式会社 測距装置、測距方法およびプロジェクタ
US7834426B2 (en) * 2007-06-29 2010-11-16 Intel Corporation High-k dual dielectric stack
EP2306497B1 (de) * 2009-10-02 2012-06-06 Imec Verfahren zur Herstellung einer Schnittstelle mit wenigen Defekten zwischen einem Dielektrikum und einer III/V-Verbindung
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
DE112017005855T5 (de) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983264A (en) * 1972-07-20 1976-09-28 Texas Instruments Incorporated Metal-semiconductor ohmic contacts and methods of fabrication
FR2454184A1 (fr) * 1979-04-10 1980-11-07 Chemla Daniel Structure de type isolant-semi-conducteur dans laquelle le semi-conducteur est un compose iii-v et l'isolant un sulfure, et procedes de fabrication de cette structure
US4354198A (en) * 1980-05-30 1982-10-12 International Business Machines Corporation Zinc-sulphide capping layer for gallium-arsenide device
US4447469A (en) * 1982-06-10 1984-05-08 Hughes Aircraft Company Process for forming sulfide layers by photochemical vapor deposition
US4843450A (en) * 1986-06-16 1989-06-27 International Business Machines Corporation Compound semiconductor interface control
FR2604826B1 (fr) * 1986-10-06 1989-01-20 France Etat Procede de formation d'une couche isolante comportant du sulfure, derives sulfures obtenus et appareillage pour la mise en oeuvre du procede

Also Published As

Publication number Publication date
DE3880019T2 (de) 1993-10-28
EP0295490A1 (de) 1988-12-21
US4811077A (en) 1989-03-07
JPS648613A (en) 1989-01-12
EP0295490B1 (de) 1993-04-07
JPH079914B2 (ja) 1995-02-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee