DE3877614T2 - Hochdichte registersatzschaltung mit hohem leistungsvermoegen. - Google Patents

Hochdichte registersatzschaltung mit hohem leistungsvermoegen.

Info

Publication number
DE3877614T2
DE3877614T2 DE19883877614 DE3877614T DE3877614T2 DE 3877614 T2 DE3877614 T2 DE 3877614T2 DE 19883877614 DE19883877614 DE 19883877614 DE 3877614 T DE3877614 T DE 3877614T DE 3877614 T2 DE3877614 T2 DE 3877614T2
Authority
DE
Germany
Prior art keywords
register circuit
density register
high density
high performance
performance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19883877614
Other languages
English (en)
Other versions
DE3877614D1 (de
Inventor
Henry Cecil Baron
Johnny James Leblanc
Thomas Martin Storey
Joseph Willard Yoder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3877614D1 publication Critical patent/DE3877614D1/de
Publication of DE3877614T2 publication Critical patent/DE3877614T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
DE19883877614 1987-04-30 1988-03-31 Hochdichte registersatzschaltung mit hohem leistungsvermoegen. Expired - Fee Related DE3877614T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4416787A 1987-04-30 1987-04-30

Publications (2)

Publication Number Publication Date
DE3877614D1 DE3877614D1 (de) 1993-03-04
DE3877614T2 true DE3877614T2 (de) 1993-07-15

Family

ID=21930865

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19883877614 Expired - Fee Related DE3877614T2 (de) 1987-04-30 1988-03-31 Hochdichte registersatzschaltung mit hohem leistungsvermoegen.

Country Status (3)

Country Link
EP (1) EP0288774B1 (de)
JP (1) JPS63276138A (de)
DE (1) DE3877614T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2215098B (en) * 1988-02-13 1992-09-09 Allan Mcintosh Memory mapping device
GB2419006B (en) * 2002-04-22 2006-06-07 Micron Technology Inc Providing a register file memory with local addressing in a SIMD parallel processor
WO2014013298A1 (en) 2012-07-20 2014-01-23 Freescale Semiconductor, Inc. Register file module and method therefor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194295A (ja) * 1984-10-16 1986-05-13 Fujitsu Ltd 半導体記憶装置
US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques

Also Published As

Publication number Publication date
EP0288774A2 (de) 1988-11-02
EP0288774B1 (de) 1993-01-20
JPS63276138A (ja) 1988-11-14
JPH0585051B2 (de) 1993-12-06
DE3877614D1 (de) 1993-03-04
EP0288774A3 (de) 1991-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee