DE3853337D1 - Mechanismus und Verfahren zur Fernverwaltung von Speichern. - Google Patents
Mechanismus und Verfahren zur Fernverwaltung von Speichern.Info
- Publication number
- DE3853337D1 DE3853337D1 DE3853337T DE3853337T DE3853337D1 DE 3853337 D1 DE3853337 D1 DE 3853337D1 DE 3853337 T DE3853337 T DE 3853337T DE 3853337 T DE3853337 T DE 3853337T DE 3853337 D1 DE3853337 D1 DE 3853337D1
- Authority
- DE
- Germany
- Prior art keywords
- remotely managing
- managing memories
- memories
- remotely
- managing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
- Computer And Data Communications (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12229687A | 1987-11-18 | 1987-11-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3853337D1 true DE3853337D1 (de) | 1995-04-20 |
DE3853337T2 DE3853337T2 (de) | 1995-10-05 |
Family
ID=22401863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19883853337 Expired - Fee Related DE3853337T2 (de) | 1987-11-18 | 1988-11-08 | Mechanismus und Verfahren zur Fernverwaltung von Speichern. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0317481B1 (de) |
JP (1) | JPH065524B2 (de) |
DE (1) | DE3853337T2 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2069711C (en) * | 1991-09-18 | 1999-11-30 | Donald Edward Carmon | Multi-media signal processor computer system |
EP0537401A1 (de) * | 1991-10-16 | 1993-04-21 | International Business Machines Corporation | Verfahren zum Nachrichtenaustausch zwischen einem gemeinschaftlichen Speicher und Datenübertragungsadaptern, unter Verwendung eines leistungsfähigen, logischen Protokolls |
US5864712A (en) * | 1995-03-17 | 1999-01-26 | Lsi Logic Corporation | Method and apparatus for controlling (N+I) I/O channels with (N) data managers in a homogenous software programmable environment |
EP0732659B1 (de) * | 1995-03-17 | 2001-08-08 | LSI Logic Corporation | (n+i) Ein/Ausgabekanälesteuerung, mit (n) Datenverwaltern, in einer homogenen Software-Programmierbetriebsumgebung |
US5655100A (en) * | 1995-03-31 | 1997-08-05 | Sun Microsystems, Inc. | Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system |
DE69628493T2 (de) * | 1995-03-31 | 2004-05-19 | Sun Microsystems, Inc., Santa Clara | Cache-kohärentes Computersystem, das Entwertungs- und Rückschreiboperationen minimiert |
DE69628079T2 (de) * | 1995-03-31 | 2004-02-26 | Sun Microsystems, Inc., Santa Clara | Mechanismus auf Systemebene zum Entwerten von Daten, die im externen Cache eines Prozessors in einem Computersystem gespeichert sind |
US5907485A (en) * | 1995-03-31 | 1999-05-25 | Sun Microsystems, Inc. | Method and apparatus for flow control in packet-switched computer system |
US5684977A (en) * | 1995-03-31 | 1997-11-04 | Sun Microsystems, Inc. | Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system |
US5657472A (en) * | 1995-03-31 | 1997-08-12 | Sun Microsystems, Inc. | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor |
US5689713A (en) * | 1995-03-31 | 1997-11-18 | Sun Microsystems, Inc. | Method and apparatus for interrupt communication in a packet-switched computer system |
US5710891A (en) * | 1995-03-31 | 1998-01-20 | Sun Microsystems, Inc. | Pipelined distributed bus arbitration system |
US5634068A (en) * | 1995-03-31 | 1997-05-27 | Sun Microsystems, Inc. | Packet switched cache coherent multiprocessor system |
JPH09212461A (ja) * | 1996-01-29 | 1997-08-15 | Internatl Business Mach Corp <Ibm> | データ転送制御方法 |
JPH1078934A (ja) * | 1996-07-01 | 1998-03-24 | Sun Microsyst Inc | パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム |
US5893165A (en) * | 1996-07-01 | 1999-04-06 | Sun Microsystems, Inc. | System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO |
US6408347B1 (en) | 1998-12-10 | 2002-06-18 | Cisco Technology, Inc. | Integrated multi-function adapters using standard interfaces through single a access point |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4145739A (en) * | 1977-06-20 | 1979-03-20 | Wang Laboratories, Inc. | Distributed data processing system |
US4325120A (en) * | 1978-12-21 | 1982-04-13 | Intel Corporation | Data processing system |
US4601586A (en) * | 1984-02-10 | 1986-07-22 | Prime Computer, Inc. | Solicited message packet transfer system |
US4649473A (en) * | 1985-06-17 | 1987-03-10 | International Business Machines Corporation | Flexible data transmission for message based protocols |
-
1988
- 1988-10-18 JP JP26072288A patent/JPH065524B2/ja not_active Expired - Lifetime
- 1988-11-08 EP EP19880480074 patent/EP0317481B1/de not_active Expired - Lifetime
- 1988-11-08 DE DE19883853337 patent/DE3853337T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0317481A2 (de) | 1989-05-24 |
EP0317481A3 (de) | 1991-01-30 |
JPH01142964A (ja) | 1989-06-05 |
DE3853337T2 (de) | 1995-10-05 |
EP0317481B1 (de) | 1995-03-15 |
JPH065524B2 (ja) | 1994-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |