DE3850339T2 - "Master/Slave"-Synchronisierungsschaltung und -verfahren. - Google Patents

"Master/Slave"-Synchronisierungsschaltung und -verfahren.

Info

Publication number
DE3850339T2
DE3850339T2 DE3850339T DE3850339T DE3850339T2 DE 3850339 T2 DE3850339 T2 DE 3850339T2 DE 3850339 T DE3850339 T DE 3850339T DE 3850339 T DE3850339 T DE 3850339T DE 3850339 T2 DE3850339 T2 DE 3850339T2
Authority
DE
Germany
Prior art keywords
slave
master
synchronization circuit
synchronization
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850339T
Other languages
English (en)
Other versions
DE3850339D1 (de
Inventor
Merle L Miller
Dale E Gulick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE3850339D1 publication Critical patent/DE3850339D1/de
Publication of DE3850339T2 publication Critical patent/DE3850339T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0685Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688Change of the master or reference, e.g. take-over or failure of the master
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0435Details
    • H04Q11/0442Exchange access circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0435Details
    • H04Q11/0471Terminal access circuits
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0685Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691Synchronisation in a TDM node
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/292Time (de)multiplexing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/299Bus
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/322Integrated circuit
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/36Synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/391Channel allocation to connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE3850339T 1987-10-21 1988-10-13 "Master/Slave"-Synchronisierungsschaltung und -verfahren. Expired - Fee Related DE3850339T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/111,475 US4860285A (en) 1987-10-21 1987-10-21 Master/slave synchronizer

Publications (2)

Publication Number Publication Date
DE3850339D1 DE3850339D1 (de) 1994-07-28
DE3850339T2 true DE3850339T2 (de) 1995-03-02

Family

ID=22338765

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850339T Expired - Fee Related DE3850339T2 (de) 1987-10-21 1988-10-13 "Master/Slave"-Synchronisierungsschaltung und -verfahren.

Country Status (4)

Country Link
US (1) US4860285A (de)
EP (1) EP0312911B1 (de)
JP (1) JP2804975B2 (de)
DE (1) DE3850339T2 (de)

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EP0518432A3 (en) * 1991-06-14 1993-11-18 Philips Nv Digital subscriber line circuit for connecting an isdn subscriber to the trunk side of a digital exchange
DE69226150T2 (de) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
GB9209570D0 (en) * 1992-05-02 1992-06-17 Texas Instruments Ltd Improvements in or relating to state machines
GB2266979A (en) * 1992-05-12 1993-11-17 Apple Computer Phase register for synchronization of multiple signal processors.
DE69331061T2 (de) * 1992-08-10 2002-06-06 Monolithic System Tech Inc Fehlertolerantes hierarchisiertes Bussystem
DE69225320T2 (de) * 1992-09-25 1998-11-19 Ibm Adapter zum Anschluss an ein "clear channel"-Übertragungsnetz
JPH06188850A (ja) * 1992-10-23 1994-07-08 Fujitsu Ltd データ転送方式及びデータ転送装置
US5428645A (en) * 1992-11-03 1995-06-27 International Business Machines Corporation Anonymous time synchronization method
US5414740A (en) * 1992-12-17 1995-05-09 International Business Machines Corporation Synchronous communication system having multiplexed information transfer and transition phases
US5774738A (en) * 1993-05-03 1998-06-30 Texas Instruments Incorporated State machines
US5689688A (en) * 1993-11-16 1997-11-18 International Business Machines Corporation Probabilistic anonymous clock synchronization method and apparatus for synchronizing a local time scale with a reference time scale
GB2293062B (en) * 1994-09-09 1996-12-04 Toshiba Kk Master-slave multiplex communication system and PLL circuit applied to the system
US5805923A (en) * 1995-05-26 1998-09-08 Sony Corporation Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used
JPH0964874A (ja) * 1995-08-28 1997-03-07 Sony Corp データ伝送方法およびデータ伝送システム
US6236675B1 (en) * 1997-03-05 2001-05-22 Paradyne Corporation Pilot tone system and method to allow continuous synchronization in multipoint networks
JPH11122207A (ja) * 1997-10-14 1999-04-30 Fujitsu Ltd 伝送装置および同期ネットワークにおける信号伝送方法
WO1999026228A1 (en) * 1997-11-18 1999-05-27 Tridium Research, Inc. Method and apparatus for phase-locking a plurality of display devices and multi-level driver for use therewith
US6023768A (en) * 1998-02-02 2000-02-08 Mcdonnell Douglas Corporation Phase locked distributed time reference for digital processing and method therefor
JP2912347B1 (ja) * 1998-04-28 1999-06-28 日本電気アイシーマイコンシステム株式会社 自営用phs親機システムにおけるisdn網とのクロック同期補正方法および回路
US6862635B1 (en) * 1998-11-13 2005-03-01 Cray Inc. Synchronization techniques in a multithreaded environment
ES2148109B1 (es) * 1998-12-30 2001-04-16 Telefonica Sa Conversor de reloj de 2.048 mhz a señal de linea a 2.048 mbit/s
US6505149B1 (en) 1999-08-02 2003-01-07 International Business Machines Corporation Method and system for verifying a source-synchronous communication interface of a device
AT407582B (de) * 1999-08-13 2001-04-25 Fts Computertechnik Gmbh Nachrichtenverteilereinheit mit integriertem guardian zur verhinderung von ''babbling idiot'' fehlern
US6557062B1 (en) * 1999-12-09 2003-04-29 Trw Inc. System and method for low-noise control of radio frequency devices
US6784881B2 (en) * 2002-01-04 2004-08-31 Sun Microsystems, Inc. Synchronizing multiple display channels
US7415002B2 (en) * 2003-10-24 2008-08-19 Brocade Communications, Inc. Circuit synchronization over asynchronous links
US8989331B2 (en) * 2006-05-31 2015-03-24 Broadcom Corporation Method and system for advance high performance bus synchronizer
US20070297433A1 (en) * 2006-06-26 2007-12-27 Mediatek Inc. Method and apparatus for double buffering
CN105009127B (zh) * 2013-02-15 2018-04-10 直观外科手术操作公司 同步机器人系统节点的系统和方法
US9706508B2 (en) * 2013-04-05 2017-07-11 Honeywell International Inc. Integrated avionics systems and methods
CN107113754B (zh) * 2014-12-16 2020-08-21 罗伯特·博世有限公司 通过非确定性网络在网络设备之间传输数据的方法

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JPS5148232A (ja) * 1974-10-23 1976-04-24 Hitachi Ltd Kurotsukuhatsuseikino dokikahoshiki
US3940558A (en) * 1975-01-31 1976-02-24 Digital Communications Corporation Remote master/slave station clock
US3959588A (en) * 1975-05-05 1976-05-25 Gte Automatic Electric Laboratories Incorporated Digital line synchronizer
FR2450008A1 (fr) * 1979-02-21 1980-09-19 Portejoie Jean Francois Circuit de synchronisation de signaux numeriques plesiochrones par justification
DE2907608A1 (de) * 1979-02-27 1980-08-28 Siemens Ag Schaltungsanordnung zur takterzeugung in fernmeldeanlagen, insbesondere zeitmultiplex-digital-vermittlungsanlagen
US4429386A (en) * 1981-01-05 1984-01-31 Siemens Corporation Buffer arrangement of a PCM exchange system
FR2513470B1 (fr) * 1981-09-18 1986-02-21 Cit Alcatel Groupe d'unites de terminaux pour autocommutateur numerique
DE3213345C2 (de) * 1982-04-08 1984-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen
US4677614A (en) * 1983-02-15 1987-06-30 Emc Controls, Inc. Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method
JPS6148256A (ja) * 1984-08-16 1986-03-08 Oki Electric Ind Co Ltd Isdn加入者線信号処理装置
JPH0640647B2 (ja) * 1985-08-01 1994-05-25 国際電信電話株式会社 Isdn端末間内線通信方式
HU194465B (en) * 1985-11-29 1988-01-28 Mta Koezponti Fiz Kutato Intez Method and device for the matrix interconnection of synchronous and/or asynchronous digital data transfer lines, advantageously in the case of serial data transfer
US4651103A (en) * 1985-12-30 1987-03-17 At&T Company Phase adjustment system
JPS62235847A (ja) * 1986-04-07 1987-10-16 Nec Corp デ−タ分岐装置
US4771418A (en) * 1986-07-28 1988-09-13 Advanced Micro Devices, Inc. Time-slot assigner multiplexer
BE905259A (nl) * 1986-08-12 1987-02-12 Bell Telephone Mfg Numeriek overdrachtsysteem.
BE1000414A7 (nl) * 1987-03-18 1988-11-22 Bell Telephone Mfg Asynchroon op basis van tijdsverdeling werkend communicatiesysteem.

Also Published As

Publication number Publication date
US4860285A (en) 1989-08-22
JPH01158848A (ja) 1989-06-21
EP0312911B1 (de) 1994-06-22
DE3850339D1 (de) 1994-07-28
JP2804975B2 (ja) 1998-09-30
EP0312911A3 (en) 1990-09-26
EP0312911A2 (de) 1989-04-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee