DE3812662A1 - Semiconductor component with superconducting connections - Google Patents

Abstract

A semiconductor component is disclosed which comprises a functional zone and a connection zone, the connection zone having superconducting connections which form an improved connection pattern with the functional zone. The functional zone is constituted by a semiconductor chip or chips with IC, LSI etc. or partial zones of an individual FET element. The improved connection pattern, either within the chip or from chip to chip, provides semiconductor components which have short transit delay times and solve various technical problems which result from the contact between the superconducting material and the semiconductor material. <IMAGE>

Description

The invention relates to semiconductor devices and more specifically, a semiconductor device which is for use in high-speed computers or large computers designed with great information processing ability is.

The semiconductor components concerned include IC or LSI semiconductor devices, which act as logic circuits and / or memory circuits used in a computer can be.

The progress in highly integrated IC components such as for example, the silicon VLSI circuit (Si-VLSI) extremely significant in recent years. Through miniaturization of the element structure are increases in the operating speed as well as increases in packing density has been developed. What is needed or desired is microfabrication technology.

In the development of micro-manufacturing techniques to reduce component dimensions, the RC distribution delay time attributed to the connection wiring resistance R and the capacitance C associated with this connection becomes non-negligible. Technical expediencies for reducing the connection resistance by wiring modification of the circuit connection structure are e.g. B. has been proposed in Japanese Patent Publication JP-B-57-46 658. In this publication, in an integrated circuit having a plurality of partial circuit element areas, a pair of connection wirings are provided for connecting the corresponding partial circuit element areas. One of the connections has a relatively high resistance and the other connection has a relatively low resistance. The two connections are connected at several points. This technique can reduce the equivalent connection resistance as compared with the conventional structure, thereby reducing the distribution delay time and allowing an improvement in the operation speed.

However, this technique can increase the resistance of any connection do not reduce the wiring itself. So of course there is a limit in reducing the connection or ver wire resistance and consequently the distribution delays time.

A concept for eliminating this limitation is Formation of connection wiring, which elements and / or chips with one another with superconducting materials connect, proposed in "Super-conductivity and its Applications ", Sangyo Tosho, May 1986, pages 161-162. By forming intermediate element or intermediate chip Connection wiring with superconducting materials the associated connection resistance can be zero can be reduced, and consequently the term or Distribution delay time can be largely reduced.

However, the inventors have in the course of research and Develop the presence of problems as below described when using superconducting materials discovered as a material for connection wiring.

A typical MOS-IC structure is shown in FIG. 1. Semiconductor elements such as MOS field effect transistors (FET) and MOS capacitors are formed in a silicon substrate 11 in active areas, which are defined by a surrounding field oxide layer 18 . In Fig. 1 on the left side of a MOS FET and shown on the right side of a MOS capacitor. The MOS-FET comprises a source region 13 and a drain region 14 , which are formed at a distance from one another in the surface of the silicon substrate 11 , furthermore a gate electrode 12 , which is located above the silicon substrate 11 via a gate oxide layer 17 between the source and drain regions 13 and 14 are formed. The MOS capacitor comprises an insulating oxide layer 17 and a capacitor electrode 16 , which is formed on the silicon substrate 11 . Interconnect layers 15 are formed on the source and drain regions 13 and 14 , as well as where wiring is desired. These electrical conductors, which are located on the substrate 11 , for example electrodes 12 and 16 and connections 15 , can be formed from superconducting material. When the semiconductor device is cooled below the critical temperature Tc of the superconducting material, the delay in the signal, which is attributed to resistances in connection wiring and routing areas, disappears. The characteristic or the operating behavior of the MOS-IC is then determined solely by the material-specific characteristics of the MOS-FET etc.

A delay time t _{w of} a wiring system can generally be expressed in terms of a connection wiring resistance R _w and a connection wiring capacitance C _w accompanying the resistance as t _w = C _w · R _w .

When using a superconducting material as the material of the connection system and by cooling the system below the critical temperature T _c , the connection wiring resistance R _w becomes zero. As a result, the delay time t _{w of} the connection system becomes zero.

If a source resistor R _{s is} present, the steepness or forward steepness g _{m of} a MOS transistor is lowered from the inherent steepness g _m °

By reducing the source resistance R _s to zero using a superconducting material, the reduction in the slope g _m due to the presence of a source resistance can be avoided.

The gate input delay time t _g can be expressed in the form of a gate capacitance C _g and a gate resistance R _g as t _g = R _g · C _g . If the gate resistance is zero, t _g = 0. So the input delay time can be neglected.

If a superconducting material is practical in a MOS IC etc. can be used, contacts between the semiconductor and cause problems for the superconducting material.

1. If a superconducting material directly on a Semiconductor surface is deposited, the metal elements such as Ba, Cu, etc., which in the superconducting material are contained in the surface and penetrate into the mass of the semiconductor element and contaminate it.

2. If a superconducting material directly with a Semiconductor body is connected can at the contact surface an energy or potential threshold is established. A current, otherwise through this contact area would flow through the diode effect due to this Potential threshold are blocked.

These technical problems discovered by the inventors pose serious obstacles in realizing practical Semiconductor components.

According to one aspect of the invention, a semiconductor device with an extremely small distribution delay time created. In the semiconductor devices according to this Aspect of the invention are circuit connection ver wires, which semiconductor chips such as ICs  and LSIs and / or semiconductor logic circuits and / or Connect semiconductor memory circuits, which in a same Substrate, that is to say in active areas, made of superconducting material or superconducting materials educated. Such semiconductor devices show one Structure in which the superconducting connection wiring is not directly connected to the active area.

According to a more limited aspect of the invention, a Semiconductor device created, in which the superconducting Wiring and the not directly with the superconducting Wiring connected active area connected are via a connection device, which consists of one of the superconducting materials different conductive Material such as a normal conductive metal is formed. When using such a structure the active area and the superconducting wiring are separated and be made independently. On this can contaminate the active area to be avoided at the time of manufacture To create semiconductor device, which is easy to manufacture is and has a high reliability.

According to another aspect of the invention, a semiconductor device created in which an active area and an electrically connected superconducting Connection wiring are physically directly connected and the impurity concentration and / or the impurity concentration concentration distribution in the semiconductor interface region of the active area connected to the superconducting connector cable wiring is in contact, be selected so that they meet predetermined conditions. According to this aspect a semiconductor component is created, in which the interface between the superconducting connector and the active area a contact with desired Characteristic or desired characteristics formed becomes.  

An advantage of the invention is that a circuit connection manufactured with extremely low resistance can be. Therefore, the distribution delay time significant due to the circuit connection wiring can be reduced to a semiconductor device higher Realize operational speed.

Another advantage of the invention is as follows: Because when connecting the superconducting connection wiring with the active area no contact between the superconducting material and the semiconductor material or no threshold to block current on the contact can exist between the two materials a semiconductor device of high reliability and excellent working parameters can be realized.

Another advantage of the invention is that it no contamination in the semiconductor interface area in the active area through direct contact between the superconducting connection wiring and the active area, or even if a contamination occurs that is attributed to the contamination Deterioration in operation speed of the active area is extremely small. In this way can create a stable operable semiconductor device be opened.

The invention can consist of different parts or different Steps and their orders exist. Embodiments the invention are described in detail below of the drawings. It shows:

Fig. 1 shows a cross section of a semiconductor MOS-IC element for explaining the invention;

Fig. 2 and 3 are cross-sections of semiconductor devices according to embodiments of the invention;

FIGS. 4 to 8 are cross sections of other embodiments in which a superconducting material in the connection wirings between the semiconductor chip of the type IC, LSI, etc. is used. Here, Figs 7 and in which a superconducting material is used in the multilayer Ver drahtungsplatte 8 special cases.

Fig. 9, 10 and 11 are diagrams for explaining the characteristics of the contact between the superconducting material and the semiconductor material, namely:

Fig. 9 shows the relationship between the impurity concentration at the semiconductor interface and the contact resistance;

Fig. 10 shows the relationship between the distance x from the interface to the p-n junction and the Übergangskriechstrom; and

Fig. 11 shows the relationship between the impurity concentration at the semiconductor interface and the height of the formed at the interface Schottky threshold;

FIG. 12A, 12B and 12C are cross sections of an embodiment of an LDD member, said figures illustrate the various steps of the manufacturing process; such as

Fig. 13 and 14 are cross sections of embodiments of a Schottky FET and -HEMT.

Referring to Fig. 2, which form a guide according to the invention from a semiconductor device showing the connecting structure will be described a superconducting link and a semiconductor of an active region between a superconducting material. The semiconductor device includes a superconducting connection part where superconducting connection wirings are formed and an active region where one or more semiconductor elements are formed. Superconducting connection wirings 21 are formed on an insulator substrate 22 by the known photolithography technique. This insulator substrate 22 may be an ordinary ceramic substrate for use in integrated circuits or a semiconductor substrate which is provided with an insulating coating. An oxidized silicon substrate is better suited than a ceramic substrate for forming fine connection structures thereon and for adapting the substrate to the semiconductor element. The material used for the superconducting connecting members 21 is e.g. B. YBa₂Cu₃O₇.

The superconducting thin film can be formed with electron beam coating or sputter coating while the substrate is being heated. Superconducting links 21 of a multilayer structure are formed by combining superconducting layers with insulating layers, e.g. B. SiO₂ insulating films, etc., using the photolithography technique, etc. The superconducting connection wiring part 26 thus formed practically has a zero distribution delay time. An active region part 27 with semiconductor circuits 24 , which are formed in a silicon crystal substrate 23 by the known micro or fine methods, is connected to the superconducting connection wirings 21 via connection metal bumps 25 . Since the superconducting connection wirings 21 of the superconducting connection wiring part 26 and the semiconductor circuits 24 of the active region part 27 do not make direct contact, the superconducting connection wiring part and the active region part can be manufactured separately, and consequently the contamination of the active region part by the element or elements comprising the superconducting material form, be reduced.

A semiconductor component according to another embodiment is described with reference to FIG. 3.

Superconducting connection wirings are formed on an insulator substrate. The superconducting members can be formed either by vacuum coating or by cheap printing. The latter process is explained here. Powder of La₂O₃, CuO and SrO₃ and a binder are mixed to form a paste. This paste is printed on an alumina ceramic substrate 32 to form structures. Then, the substrate 32 is sintered in an oxygen atmosphere at 1100 ° C. for ten hours to form superconducting connection wirings 31 . Semiconductor circuits 34 are formed in silicon crystal substrates 33 using the known fine processes to form active regions 37 . These active regions 37 and the separately fabricated superconducting connection wiring part 36 are connected to each other with metal wires 35 such as gold wires, etc., to create a semiconductor device. Advantages similar to those of the embodiment of FIG. 2 can be achieved with this embodiment. The metal wires 35 can be formed from a superconducting material.

Another embodiment will be described with reference to FIG. 4. A structure of superconducting connection wirings 41 is formed on an insulator substrate 42 made of ceramic or resin in a similar manner as in the case of Fig. 2. On the superconducting connection wiring part 46 thus manufactured, IC chips 44 are attached by an adhesive 43 to act as active areas serve. Bond pads on the IC chips 44 are connected to the superconducting connection wirings 41 by means of the known wire bonding technique to complete a semiconductor device. In this embodiment, too, no direct contact is formed between the semiconductor material of the IC chips, which are the active regions, and the superconducting material of the superconducting connection wiring 41 .

With reference to FIGS. 5A and 5B are still further implementation form of compounds described in which so-called "flip-chip packages" are. In Fig. 5A superconducting connection wirings are formed on a ceramic or a glass substrate 52 51st Then, semiconductor chips 57 with ICs (Integrated Circuit) or LSI (Large-scale Integration, etc.) with solder or semiconducting resin 55 are attached to the substrate 52 . Fig. 5B also shows a flip-chip semiconductor device. An oxide insulating layer 53 made of SiO₂, etc. is formed on a silicon substrate 52 to form an insulator substrate. Other parts of the semiconductor device of FIG. 5B are similar to those of FIG. 5A.

Another embodiment will be described with reference to FIG. 6. In the figure, reference numeral 62 denotes conductive support members, called lead frames. A wiring layer 61-1 on which a superconducting wiring structure is formed is attached with an insulating adhesive layer 63 on the lead frame. Chips 64 with ICs, transistors, etc. are mounted on this wiring layer 61-1 in a manner similar to that in the case shown in FIG. 4. The respective chips 64 and the superconducting connection wirings are connected using wires 65 made of gold, etc. The figure shows a case in which wire bonding is performed using bonding pads 61-2 formed on the wiring layer 61-1 . The semiconductor device of this type, although not shown in the figure, is typically cast in a passivation material such as resin such that it is disposed between the lead frames 62 on the right and left sides. In this embodiment, too, no direct contact is formed between the superconducting wirings and the semiconductor of the chips. They are always connected via a connecting device which is formed from a conductive material, such as gold wire, other than the superconducting materials.

Embodiments using the so-called "multi-layer wiring board" will be described with reference to FIGS. 7 and 8. In Fig. 7, a compound superconducting wiring part 70 having comprising a multi-layer three-dimensional wiring structure formed by 72 layers 78 are combined organic insulating material such as poly-imides and superconducting connection wirings 71 on an existing semiconductor material such as silicon substrate. So-called "contact holes" 76 are formed at selected locations to connect the respective superconducting connection wirings 71 , a ground electrode 73 formed on the lower surface of the substrate 72 and the conductive regions 77 which form the ground lines to conductive members which fill the contact holes or cover. The superconducting connection wirings 71 are structured from the respective layers of superconducting material in the superconducting connection wiring part 70 by the known method such as sputtering. Several chips 74 , e.g. B. IC, LSI, etc., which are the active areas, are mounted on the superconducting connection wiring part 70 via bonding pads 79 and bumps 75-1 . The chip 74f a is also connected to the superconducting wirings 71 via gold wires 75-2 , whereby it is connected to a power source (not shown). The conductive material that fills or covers the contact holes 76 can be a superconducting material.

The semiconductor device of Fig. 8 uses a ceramic multilayer wiring board. Similar to the component of FIG. 7, the semiconductor component of FIG. 8 has a superconducting connecting part 80 , which is formed from multi-layer superconducting wirings 81-1 , contact holes 81-2 and multi-layer insulating layers 82 . In deviation from Fig. 7, the insulating layers 82 are formed of ceramic. Therefore, even without the Si substrate 72 of FIG. 7, the respective superconducting wirings 81-1 and the contact holes (also the superconducting material) 81-2 are firmly supported by the rigidity of the insulating layers 82 . Furthermore, in this embodiment, superconducting electrodes 86 for the external connections are formed on the front surface and rear surface of the superconducting connection part 80 . Some of the superconducting electrodes 86 are coated with an insulating material 83 . Predetermined sections of these superconducting electrodes 86 are connected to a plurality of chips, 84 , IC, etc., via conductor members 85, such as solder bumps. Fig. 8 shows only 84 chips on the lower surface. It goes without saying that chips can also be provided on the upper surface.

Although in the above-described embodiments only superconducting connection wiring in the superconducting Connection part trained, but it can other components can also be introduced. The superconducting Connector can be on a semiconductor wafer such as a Si substrate or a composite Semiconductor substrate such as GaAs formed will. Furthermore, elements can also be in the wafer such as diodes, transistors, etc. are formed. One of important points in the embodiments described above is that the semiconductor material in the active area and the superconducting connecting links do not make direct contact. When building the separate Manufacture of the superconducting connecting part and of the active areas, as above in connection with the described embodiments, brings it also has an advantage in that the metal element or the metal elements, which superconducting connecting links form, can be prevented from doing so Penetrate semiconductor material when the superconducting Links are made.  

In the foregoing embodiments, structures are described which use superconducting connectors for the wiring between chips such as IC, LSI, etc. The invention is not limited to such structures. The connections of the semiconductor components can comprise connection wiring in a discrete component or in a single element such as an FET (field-effect transistor), furthermore connection wiring for connecting circuit elements, e.g. B. connection wiring in an IC chip, connection wiring for connecting IC chips to each other as described above, or connection wiring such as lead frame, as shown in Fig. 6. Significant in the invention is the fact that in a semiconductor device, those interconnect wirings where the distribution delay time becomes a problem are made of one or more superconducting materials regardless of the location of the interconnect wiring and an improvement in the connection of the superconducting material the active area (e.g. FET, IC chip, etc.) is achieved. The construction of this improvement has been described above in terms of aspects and advantages of the invention, and a particular type of construction has been described in the foregoing embodiments. A structure of a different kind will now be described below. The following embodiments are intended for connection wiring in semiconductor elements.

In the following embodiments, implementations regarding the wiring structure in a single element described in detail. It is obvious that the following Execution forms in combination with the previous ones Embodiments can be used.

The inventive discovery will be described with reference to FIG. 9, which improves the contact between the superconducting material and the semiconductor material. Fig. 9 explains the relationship of the contact resistance (Ω / cm²) of the contact formed by a superconducting material of a perovskite (?) Compound of yttrium, barium, copper and oxygen with silicon at a temperature below the critical temperature Tc to the impurity concentration at the interface in a p-type or n-type silicon. As can be seen from the figure, the contact resistance decreases rapidly at impurity concentrations equal to or greater than about 1.5 × 10¹⁸ cm ^-3 . The interface impurity concentration of the semiconductor material can preferably be selected in this range. Furthermore, in order to obtain a practical value of the contact resistance, 10 ^-6 Ω / cm² or less, the impurity concentration can be selected more preferably at or above 4 × 10¹⁸ cm ^-3 regardless of the type of conductivity. The contact resistance actually shows a temperature dependency, but the data shown in this embodiment generally apply generally to the temperatures at the critical temperature Tc or below. Namely, the relationship of Fig. 9 applies generally generally at temperatures not higher than Tc , and hence the impurity concentration at the semiconductor interface can be determined regardless of the working temperature to lower the contact resistance below a certain value.

Another characteristic regarding the contact between the superconductor and the semiconductor is described with reference to FIG. 10. This figure shows measurement results on the relationship between the distance x from the interface between the superconductor and the semiconductor to the pn junction and the reverse current I _{L of} the transition when a reverse bias of 5 V is applied. It can be seen that the reverse current is good and at is a substantially constant value when x is 0.02 µm or more. Therefore, the distance x from the interface between the superconductor and the semiconductor to the pn junction should preferably be selected to be at least equal to 0.02 μm.

The breakdown voltage of the transition increases as the distance x increases. If the distance x is about 0.02 µm, the breakdown voltage is 3 to 4 V. If the distance x is increased to about 0.07 µm, the breakdown voltage becomes sufficiently large, ie about 10 V. This is because the Impurity concentration at the interface between the superconductor and the semiconductor is sufficiently high, that is, not less than 1 × 10¹⁹ cm ^-3 and the pn junction section is on the order of 1 × 10¹⁵ cm ^-3 . So the field intensity distribution is sharp and a breakthrough can easily occur.

The results shown in this embodiment can similarly apply to n⁺p transitions and p⁺n transitions.

A Schottky contact between a superconductor and a semiconductor is described with reference to FIG. 11. The figure shows the relationship of the height of the Schottky junction formed at the interface between the superconductor and the semiconductor to the impurity concentration in the semiconductor. As can be seen from the figure, the height of the Schottky barrier layer can be freely decided by controlling the impurity concentration. The junction height begins to decrease sharply when the impurity ^{concentration} rises above about 1 × 10¹⁷ cm ^-3 . The superconducting material used in this embodiment is a yttorium barium copper oxide. It has been found that when using other superconducting materials, relationships occur which are somewhat different, but are essentially similar to the relationship in FIG. 11. Therefore, it becomes possible to generate a Schottky contact from predetermined characteristics. Good contact characteristics could be achieved in particular with interface impurity concentrations of 6 × 10¹⁷ cm ^-3 or less. It has been shown that above this concentration in particular the blocking characteristic of the transition deteriorated and that such transitions were not very suitable for practical applications.

An embodiment of a component with a lightly doped drain electrode (LDD) is described with reference to FIGS. 12A, 12B and 12C. This FET is fabricated using the characteristics shown in FIGS. 9 and / or 10.

In Fig. 12A, an element - insulation oxide film 122 - having a thickness of 0.06 µm is formed on a p-type ( 100 ) - oriented silicon substrate 121 with a resistivity of 10 Ω · cm. A gate oxide film 123 of a thickness of 20 μm, a polycrystalline silicon gate 124 of a thickness of 0.35 μm, lateral spacers 125 and a lightly doped diffusion region 126 of 10¹⁷ cm ^-3 are formed by the known methods.

In Fig. 12B, after a part of the gate oxide film 123 shown in Fig. 12A has been removed, a film of a superconducting material (an yttrium-barium-copper-oxygen compound) is sputter-deposited to a thickness of about 0.02 µm Arsenic is ion-implanted by ion implantation at an accelerating energy of 150 keV up to a dose of 1 × 10¹⁶ cm ^-2 , and the assembly is heat-treated by short-time annealing at 1000 ° C for ten seconds to form a superconducting film 127 and n⁺ diffusion areas 128 to generate. Here, the transition depth of the n⁺ diffusion region 128 was 0.01 µm, and the arsenic concentration at the interface with the superconducting film 127 was about 3 × 10²⁰cm ^-3 .

In the present embodiment, n⁺ areas formed after a superconducting material is deposited was. It is also possible to form n⁺ areas first  and then form a superconducting film. The latter is advantageous if flat transitions are to be formed because the conditions for activating the fault point are arbitrary can be chosen.

In Fig. 12C, an interlayer insulating film 129 made of phosphorus silicate glass (PSG) and connection wiring members 120 made of a superconducting material are formed on the structure of Fig. 12B to complete a semiconductor device. In this embodiment, a superconducting material is used to form the connection wirings 120 . Good results could also be achieved using conventional aluminum or aluminum alloy wiring. In particular for high current density LSIs, it is advantageous to form the connection wirings with aluminum or aluminum alloy. This is because the superconducting material of the yttrium-barium-copper-oxygen system has a maximum permissible current density of at most about 10⁵ A / cm². This is not suitable for high current LSIs. It is possible to use a superconducting material as the gate electrode.

The operating behavior of transistors and ICs, which Using transistors has been significantly improved when used of superconducting material or superconducting Materials for the control electrode (gate), the source Electrode, the drain electrode and the wiring layers. For example, if a delay time is one with the conventional minimum dimensions of 1.25 µm Control electrode was 0.4 ns, created a similar control electrode when using a superconducting material a gate delay time for all conductors of the transistor of 0.2 ns, which is twice the conventional Ge is dizziness.  

Referring to Figs. 13 and 14 embodiments of the Schottky gate FET will be described.

Fig. 13 shows in cross section the structure of a MES-FET. Silicon ions were implanted into a surface area of a semi-ionizing GaAs substrate 131 where an FET was to be formed with an accelerating energy of 75 keV and a dose of 1 × 10¹³ cm ^-2 by ion implantation around a channel layer 132 with an impurity concentration of 2 × 10¹⁷ cm ^-3 and a depth of 0.15 µm to form. A superconducting gate or control electrode 133 of a yttrium-barium-copper-oxygen system material was sputter-deposited on the GaAs substrate 131 to a thickness of 0.3 µm. Then, silicon ions were implanted into the GaAs substrate 131 by ion implantation with an acceleration energy of 150 keV and a dose of 1 × 10¹⁴ cm ^-2 , using the superconducting gate electrode 133 as a mask to cover source / drain regions 134 with a Impurity concentration of 1 × 10¹⁸ cm ^-3 and a depth of 0.3 microns to form. Then an insulating film 135 was applied and processed to have vias. Then, a triple layer of gold germanium (Au-Ge), nickel (Ni) and gold (Au) formed source / drain electrodes 136 with a thickness of 0.3 µm by lifting. The barrier height of the Schottky contact formed from the channel layer 132 and the superconducting gate electrode 133 was about 0.4 V, and the threshold voltage of the MES FET was 0.2 V.

While the conventional MES-FET (metal semiconductor FET) when using a gate electrode made of tungsten silicide (WSi₂) with a gate length of 0.8 µm has a gate delay time of 50 ps, the MES-FET had this Embodiment using similar gate length a superconducting gate electrode an improved delay time from 30 ps.  

An embodiment of a high-electron mobility transistor (HEMT) is described with reference to FIG. 14. The figure shows the cross-sectional structure of a HEMT element. On a semi-insulating GaAs substrate 141 , a GaAs layer 147 0.5 µm thick and an n-type AlGaAs layer 148 0.06 µm thick were grown epitaxially to make a heterojunction at the AlGaAs interface to build. A superconducting gate electrode 143 formed of a superconducting film made of yttrium-barium-copper-oxygen system material and having a thickness of 0.3 µm was applied by sputtering. Then an insulating layer 145 was applied around the superconducting gate electrode 143 . Where the insulating film 145 was not formed, source / drain regions 144 of heavily doped n-type GaAs layers with a thickness of 0.2 μm were formed by selective epitaxial growth on the substrate. Source / drain electrodes 146 were formed on these source / drain regions 144 . Here, the n-type AlGaAs layer 148 had a donor concentration of 5 × 10¹⁷ cm ^-3 , and the barrier layer height of the Schottky contact with the superconducting gate electrode was approximately 0.6 V.

In the semiconductor element of this type, the electrons (carriers) supplied from the n-type AlGaAs layer 148 into the GaAs layer 147 form a two-dimensional gas which transports in the vicinity of the heterojunction 149 at high speed.

The HEMT element of this embodiment with a gate length of 0.9 µm showed an improved characteristic data Threshold voltage of -0.4 V and a gain factor 600 mS / mm. It also resulted in a gate delay time of 5 ps, which is about half the value of the conventional one HEMT element is a gate electrode made of titanium platinum (Ti-Pt) used.  

Instead of the n-type semiconductor layer 148 , a p-type semiconductor layer can be used to form an element that transports positive holes at high speed. In such a case, with respect to the relationship between the superconducting gate electrode 143 and the semiconductor layer 148, the impurity concentration in the semiconductor layer 148 at the contact portion of the superconducting gate electrode is preferably selected to be 6 × 10¹⁷ cm ^-3 or less as described in connection with FIG. 11.

Although the invention is primarily with reference to Silicon or GaAs devices have been described, it is understood that other semiconductors are also used including materials made of GaAlAs, InP, InGaAsP, and the like.

Furthermore, the invention has been described with reference to YBa₂Cu₃O₇ as a superconducting material; it should be noted that other superconducting materials can also be used, including materials made from RE M₂Cu₃O _{7- w} , where RE is at least one from La, Y, Sr, Yb, Lu, Tm, Dy, Sc, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Ho and Er is selected material and M is at least one of Ba, Sr, Ca and K.

(These have a so-called oxygen deficiency perovskite structure or a K₂NiF₄ structure on and are high temperature superconducting materials which Superconductivity at temperatures close to the liquid Show nitrogen temperature.)

The invention is based on preferred embodiments have been described. Obviously, the specialist Variations in reading and understanding the description come to mind. The invention includes within the scope of the claims any such changes.

Claims (18)

1. Semiconductor component, characterized by at least one functional region ( 27; 37; 44; 57; 64; 74; 84; 121, 126, 128 ) with a semiconductor region ( 24; 33; 44; 57; 64; 74; 84; 121, 126 ), which works electrically through an electric field and / or electric current, a connection area ( 26; 36; 46; 56; 61-1, 61-2, 62, 63; 70, 72, 73; 80; 127 , 120, 129 ) with superconducting connections ( 21; 31; 41; 51; 61-1, 61-2; 71; 81-1, 81-2; 127 ) which give the semiconductor area the electric field and / or the electric current supply, as well as devices ( 25; 35; 45; 55; 58; 65; 75-1, 75-2; 85; 128 ) for connecting the semiconductor region to the superconducting connections in such a way that no direct contact of the superconducting connections with the Semiconductor area is manufactured. 2. Component according to claim 1, characterized in that the device for connecting consists of metal. 3. Component according to claim 1, characterized in that the functional area is an IC chip or an LSI chip is. 4. The component according to claim 1, characterized in that the connection region comprises a substrate ( 23; 32; 42; 52; 62; 72; 82 ) which carries the superconducting connections. 5. The component according to claim 1, characterized in that the superconducting compounds have a multilayer Have structure. 6. The component according to claim 1, characterized in that the device for connecting a wire bonding device and / or a flip chip bonding device. 7. The component according to claim 4, characterized in that that the substrate is made of glass or ceramic. 8. Semiconductor component, characterized by a substrate ( 121 ), a current path region ( 126 ) formed on the substrate, a device ( 124 ) for controlling the current in the current path region, at least one superconducting connection ( 120 ) which supplies current to the current path region, and at least one semiconductor region ( 128 ) which is arranged between the current path region and the superconducting connection in such a way that no direct contact is established between the current path region and the superconducting connection. 9. The component according to claim 8, characterized in that the semiconductor region has an impurity concentration of not less than 1.5 × 10¹⁸cm ^-3 . 10. The component according to claim 9, characterized in that the semiconductor region has a thickness of no less than 0.02 µm. 11. Semiconductor component, characterized by a substrate ( 131; 141 ), a stack structure formed on the substrate, which forms an active region ( 132; 148, 147 ), a connection region ( 133, 136; 143, 146 ), which is connected to is connected to the stack structure and has at least one electrode ( 133; 143 ) made of superconducting material, through which an electric field is supplied to the active region, at least a part of the active region with which the electrode is in contact no longer having an impurity concentration than 6 × 10¹⁷ cm ^-3 . 12. The component according to claim 11, characterized in that that the electrode and the active area have a Schottky Make contact. 13. The component according to claim 11, characterized in that the stack structure comprises a substantially non-doped semiconductor layer ( 147 ), where current carriers move as a two-dimensional gas. 14. Semiconductor component, characterized by at least a semiconductor chip with semiconductor elements formed therein, which carries first bond areas that from consist of electrically conductive material and on a Surface of the chip are arranged, connecting devices, which connection wiring made of superconducting Have material and second bond areas have, as well as guide members, which from an electrical conductive material and the first bond areas electrically connect to the second bond areas. 15. The component according to claim 14, characterized in that the connector means around an insulator substrate  summarizes on which the connection wiring is formed are. 16. The component according to claim 15, characterized in that a plurality of semiconductor chips is provided. 17. The component according to claim 16, characterized in that that the guide members include metal bumps. 18. The component according to claim 16, characterized in that that the plurality of semiconductor chips on the insulator substrate is worn and the guide links metal wires include.