GB2211662A - Multichip carriers with superconductive interconnections - Google Patents

Abstract

A multichip carrier (11) with integral cooling comprises superconductive ceramic chip interconnections (22) embedded in a substrate (12) supporting chips (21). Highly compressed gas, fed through channels (15) in the substrate, is expanded into wells (13) situated beneath the chips. The expanded gas reduces in temperature and cools the chips by direct impingement thereon. Gas is exhausted from the wells via outlet channels (16, 17) which extend within the substrate to cool the entire substrate including the embedded superconductive ceramic interconnections. <IMAGE>

Description

MULTICHIP CARRIERS The present invention relates to multichip carriers and in particular to a multichip carrier with integral cooling.

Current solid state circuit technology, such as for example CMOS logic, is operable at higher speeds when cooled to a very low temperature. Performances can be increased by a factor of 2 at temperatures of 0 approximately 70 K. The lower temperature also allows higher integration densities on CMOS chips as local heating effects are reduced. Furthermore, thermal noise in infra red detectors and CMOS analogue devices is substantially reduced and the parameter stability of the devices is improved.

Other devices which require very low temperatures for their efficient operation are superconductor devices which include, for example, Josephson junctions and Meissner effect detectors.

Although, on a multichip carrier, interchip delays are reduced by the physical proximity of the chips, it is nevertheless desirable to reduce this still further.

One object of the present invention is to provide a cooled multichip carrier which enables low temperature semiconductor devices to be operated with increased efficiency.

Another object of the present invention is to provide a cooled multichip carrier with reduced interchip delays.

According to the present invention a multichip carrier includes: a substrate; a plurality of ciruit chips mounted on the substrate; interconnections between the circuit chips formed by superconductive ceramic material supported by the substrate; and cooling means effective to lower the temperature of the substrate to a level below the superconductivity threshold.

Preferably the substrate includes a plurality of wells formed in'a first face, each well having a high pressure gas inlet passage and a low pressure gas outlet passage formed in the substrate; and said circuit chips are mounted on the first face, one covering each well; the arrangement being such that, when highly compressed gas fed through the inlet passages enters the wells, the gas expands and reduces in temperature to thereby cool the circuit chips by direct impingement thereon, the expanded gas also cooling the entire substrate by conduction as it passes through the outlet passages.

A multichip carrier will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a sectional view of part of a multichip carrier; Figure 2 shows a substrate with circuit chips mounted thereon and Figure 3 shows a sectional view of part of the substrate containing an embedded superconductor.

Referring to Figures 1 and 2 of the drawings, a chip carrier 11, of the so-called 'cavity down' type, comprises a non-conductive substrate 12 which may, for example, be formed from a ceramic material. A number of cavities or wells 13 (only one of which is shown in Figure 1) are formed in the substrate 12 and each of the wells 13 is connected to a common inlet port 14 by a high pressure microbore passage 15. Each well 13 also has a low pressure outlet passage 16 leading into a common passage 17 which has a vent 18 leading to the atmosphere. The high pressure microbore passages 15 and the low pressure outlet passages 16, 17 are formed by etching the required channels and recesses in the surface 19 of the substrate 12 and bonding a lid 20 to the surface 19 to complete the passages.

A circuit chip 21 is secured over each of the wells 13 as shown in Figure 1. Conductors 22 of superconductive ceramic material are embedded in the substrate 12 and connections 23 are bonded between the chip circuitry and the conductors 23 using a tape automated bonding process (TAB). The conductors 22 and the connections 23 together form interconnections between the circuit chips 21.

The conductors 22 are formed by chemically etching channels in the substrate 12 and packing the channels with a suitable compound, such as for example, yttrium or copper oxide based ceramic. Finally, the compound is sintered under pressure to produce the finished conductors. To ensure that the conductors do not become loose in their channels due to thermal stress which may be introduced during operation, the sides of the channels are tapered as shown in Figure 3.

An alternative method of forming the conductors 22 is by plasma deposition of the conductor material on to the substrate and etching the conductive material into the surface of the substrate 12.

A lower lid 24 is bonded to the underside of the chip carrier to complete the sealing of the device.

Connections (not shown) between the chip carrier and external circuits may be provided by pins, flying leads or by using a so-called leadless interconnect arrangement. All of these techniques are well known and thus are not described in detail.

For higher cooling efficiency it is preferred that the entire chip carrier is surrounded by a thermal insulator.

In operation, gas under high pressure is introduced into the common inlet port 14. The gas may be air or nitrogen which is cleaned by the removal of all hydrocarbons, water vapour and CO2 and is introduced into the port 14 at a pressure of approximately 3 x 10 - 4 x 10 NT/M2. Because the microbore passages 15 are very small, the gas flow rate is very low and thus, when the gas enters the wells 13 it expands, reduces in temperature and liquifies.

The liquified gas impinges on the undersides of the circuit chips 21 to cool them by direct contact therewith. The gas also impinges on the sides and the bases of the wells 13 to cool the substrate 12 in the region of the wells.

It is preferred that the microbore passages 15 are rectangular in form and have dimensions, for example, of 5-500 microns x 6 microns with the largest dimension extending into the substrate 12. These extremely small dimensions are conducive to laminar gas flow and ensure that the total pressure exerted on the lid 20 by the incoming high pressure gas is not so high as to impose undue strain on the lid. The inlet passages 15 are arranged to radiate outwardly from the central inlet port 14 to evenly distribute the pressure exerted on the lid 20. It should be noted that the low pressure output passage 17 extends between the radiating channels 15 and within a substantial part of the substrate 12. This arrangement enables the exhausting low pressure gas to pre-cool the high pressure gas entering through the passages 15 and also cools the substrate as a whole.Due to conduction within the substrate 12, the cooling in the regions of the wells together with the cooling of the channels 17 ensure that the substrate 12 including the conductors 22 is evenly cooled throughout.

It has been found that the described arrangement will cope with a heat dissipation of up to 0.5 watts per chip and is effective to maintain the temperature of the chip at, less than 700K, a level at which the chip performance is increased by a factor of 2. Furthermore, the superconductive conductors 22 are cooled to a temperature level below the superconducting threshold at which level interchip delays are considerably reduced. In order to attain such performances it is preferable that the substrate is cooled before the chips are operated in a stable state as the cooling is not so effective if the chip temperature is allowed to rise first.

Even lower cooling temperatures can be achieved by using one of the inert gases instead of air or nitrogen as has been described. However, the expense of such a gas would require that a closed circuit system is employed in which the exhausted gases are collected and recirculated and would thus add to the complexity of the system.

The efficiency of the device could be further improved by the provision of a pre-cooler for the high pressure gas. Such a pre-cooler would operate by the same principal as the described cooler formed in the substrate but would be contained in a separate housing.

One way of reducing the throughput of gas in a venting-to-atmosphere arrangement is to provide a needle valve (not shown) in each well at the inlet to control the rate of flow. Such a needle valve could be operated by, for example, a float or a temperature sensitive bimetal strip.

The described example is suitable for use with CMOS logic, infra red detectors, CMOS digital eig!i processors and superconductive ceramics. It provides the advantages of entire substrate cooling, thus reducing thermal stress, low interchip delays and low noise for high frequency thermal imaging applications.

If infra red detectors are incorporated in the chip carrier, a transparent window is incorporated in the bottom lid 24. Such a window would require to be transparent to the required operational frequencies and could, for example, be formed from germanium or selenium sulphide.

It will be realised from the foregoing that the effectiveness of the substrate cooling is dependant upon the following factors: (a) the heat load of the active devices (b) the thermal conductivity of the chip carrier (c) the microbore size (d) the pressure differential, and (e) the type of gas used Although a multichip carrier has been described, it is envisaged that the invention could be applied to other forms of circuit structure, for example, CMOS silicon wafers. In this case the inlet/exhaust channels and the wells could be etched in a non-active lower wafer and an active upper semiconductor wafer bonded to the lower wafer.

Claims (8)

CLAIMS:

1. A multichip carrier ir#(luJ\iflg; a substrate; a plurality of circuit chips mounted on the substrate; interconnections between the circuit chips formed by superconductive ceramic material supported by the substrate; and cooling means effective to lower the temperature of the substrate to a level below the superconductivity threshold.

2. A multichip carrier as claimed in Claim 1 wherein the substrate includes a plurality of wells formed in a first face, each well having a high pressure gas inlet passage and a low pressure gas outlet passage; and wherein said circuit chips are mounted on the first face, one covering each well; the arrangement being such that, when highly compressed gas fed through the inlet passages enters the wells, the gas expands and reduces in temperature to thereby cool the circuit chips by direct impingement thereon, the expanded gas also cooling the entire substrate by conduction as it passes through the outlet passages.

3. A multichip carrier as claimed in claim 2, in which the high pressure gas inlet passages include micro passages radiating outwardly from a central inlet port ,* and the gas outlet passages include portions extending between the radiating passages and within a substantial portion of the substrate.

4. A multichip carrier as claimed in claim 2 or 3, in which the superconductive ceramic interconnections are embedded in said first face of the substrate.

5. A multichip carrier as claimed in claim 2, 3 or 4, in which the inlet and outlet passages are formed as open channels in a second face of the substrate opposite said first face, and a sealing member in the form of a lid is secured over said second face.

6. A multichip carrier as claimed in any of claims 2 - 5, including a control valve situated in the gas inlet passage of each well.

7. A multichip carrier as claimed in any preceding claim, in which at least some of the circuit chips include infra red detectors.

8. A multichip carrier constructed and arranged to operate substantially as hereinbefore described with reference to the accompanying drawings.