DE3781873D1 - Rekonfigurierbare rechenanordnung. - Google Patents

Rekonfigurierbare rechenanordnung.

Info

Publication number
DE3781873D1
DE3781873D1 DE8787402431T DE3781873T DE3781873D1 DE 3781873 D1 DE3781873 D1 DE 3781873D1 DE 8787402431 T DE8787402431 T DE 8787402431T DE 3781873 T DE3781873 T DE 3781873T DE 3781873 D1 DE3781873 D1 DE 3781873D1
Authority
DE
Germany
Prior art keywords
computing arrangement
reconfigurable computing
reconfigurable
arrangement
computing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787402431T
Other languages
English (en)
Other versions
DE3781873T2 (de
Inventor
Corlieu Patrick De
Michel Prevost
Chene Arnaud Du
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of DE3781873D1 publication Critical patent/DE3781873D1/de
Application granted granted Critical
Publication of DE3781873T2 publication Critical patent/DE3781873T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2041—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with more than one idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2048—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share neither address space nor persistent storage
DE8787402431T 1986-10-31 1987-10-28 Rekonfigurierbare rechenanordnung. Expired - Fee Related DE3781873T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8615241A FR2606184B1 (fr) 1986-10-31 1986-10-31 Dispositif de calcul reconfigurable

Publications (2)

Publication Number Publication Date
DE3781873D1 true DE3781873D1 (de) 1992-10-29
DE3781873T2 DE3781873T2 (de) 1993-02-11

Family

ID=9340434

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787402431T Expired - Fee Related DE3781873T2 (de) 1986-10-31 1987-10-28 Rekonfigurierbare rechenanordnung.

Country Status (5)

Country Link
US (1) US4891810A (de)
EP (1) EP0272165B1 (de)
JP (1) JPS63141139A (de)
DE (1) DE3781873T2 (de)
FR (1) FR2606184B1 (de)

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US5513313A (en) * 1993-01-19 1996-04-30 International Business Machines Corporation Method for generating hierarchical fault-tolerant mesh architectures
US5515501A (en) * 1994-01-21 1996-05-07 Unisys Corporation Redundant maintenance architecture
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US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
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US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
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DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) * 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) * 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
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US6219467B1 (en) * 1997-07-15 2001-04-17 Fuji Photo Film Co. Ltd. Image processing device
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6067633A (en) * 1998-03-31 2000-05-23 International Business Machines Corp Design and methodology for manufacturing data processing systems having multiple processors
WO2002013000A2 (de) 2000-06-13 2002-02-14 Pact Informationstechnologie Gmbh Pipeline ct-protokolle und -kommunikation
AU5805300A (en) 1999-06-10 2001-01-02 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) * 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US6449209B1 (en) * 2001-01-19 2002-09-10 Samsung Electronics Co., Ltd. Semiconductor memory device comprising more than two internal banks of different sizes
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US20090300262A1 (en) * 2001-03-05 2009-12-03 Martin Vorbach Methods and devices for treating and/or processing data
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
EP2224330B1 (de) * 2001-06-20 2012-05-09 Krass, Maren Verfahren und gerät zum partitionieren von grossen rechnerprogrammen
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) * 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US20050132344A1 (en) * 2002-01-18 2005-06-16 Martin Vorbach Method of compilation
WO2003060747A2 (de) * 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US7017074B2 (en) * 2002-03-12 2006-03-21 Sun Microsystems, Inc. System architecture providing redundant components to improve die yields and system reliability
US20060075211A1 (en) * 2002-03-21 2006-04-06 Martin Vorbach Method and device for data processing
US8914590B2 (en) * 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) * 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
US20110238948A1 (en) * 2002-08-07 2011-09-29 Martin Vorbach Method and device for coupling a data processing unit and a data processing array
US20070083730A1 (en) * 2003-06-17 2007-04-12 Martin Vorbach Data processing device and method
AU2003286131A1 (en) * 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
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JP2006524850A (ja) * 2003-04-04 2006-11-02 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データ処理方法およびデータ処理装置
JP4700611B2 (ja) * 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
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Also Published As

Publication number Publication date
JPS63141139A (ja) 1988-06-13
FR2606184B1 (fr) 1991-11-29
DE3781873T2 (de) 1993-02-11
US4891810A (en) 1990-01-02
EP0272165B1 (de) 1992-09-23
FR2606184A1 (fr) 1988-05-06
EP0272165A1 (de) 1988-06-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee