DE3688049D1 - Signaleingangsschaltung mit signalverriegelungsfunktion. - Google Patents

Signaleingangsschaltung mit signalverriegelungsfunktion.

Info

Publication number
DE3688049D1
DE3688049D1 DE8686117063T DE3688049T DE3688049D1 DE 3688049 D1 DE3688049 D1 DE 3688049D1 DE 8686117063 T DE8686117063 T DE 8686117063T DE 3688049 T DE3688049 T DE 3688049T DE 3688049 D1 DE3688049 D1 DE 3688049D1
Authority
DE
Germany
Prior art keywords
signal
locking function
input switching
signal input
signal locking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686117063T
Other languages
English (en)
Other versions
DE3688049T2 (de
Inventor
Kazuo Nakaizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3688049D1 publication Critical patent/DE3688049D1/de
Publication of DE3688049T2 publication Critical patent/DE3688049T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
DE8686117063T 1985-12-06 1986-12-08 Signaleingangsschaltung mit signalverriegelungsfunktion. Expired - Fee Related DE3688049T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60275421A JPH0817028B2 (ja) 1985-12-06 1985-12-06 リフレッシュ信号入力回路

Publications (2)

Publication Number Publication Date
DE3688049D1 true DE3688049D1 (de) 1993-04-22
DE3688049T2 DE3688049T2 (de) 1993-09-09

Family

ID=17555273

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686117063T Expired - Fee Related DE3688049T2 (de) 1985-12-06 1986-12-08 Signaleingangsschaltung mit signalverriegelungsfunktion.

Country Status (4)

Country Link
US (1) US4825415A (de)
EP (1) EP0226929B1 (de)
JP (1) JPH0817028B2 (de)
DE (1) DE3688049T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2764908B2 (ja) * 1988-02-04 1998-06-11 日本電気株式会社 カスケード・バッファ回路
EP0552667B1 (de) * 1992-01-22 1999-04-21 Enhanced Memory Systems, Inc. DRAM mit integrierten Registern
US5754879A (en) * 1996-09-23 1998-05-19 Motorola, Inc. Integrated circuit for external bus interface having programmable mode select by selectively bonding one of the bond pads to a reset terminal via a conductive wire
US5914844A (en) * 1997-10-14 1999-06-22 Cypress Semiconductor Corp. Overvoltage-tolerant input-output buffers having a switch configured to isolate a pull up transistor from a voltage supply
US6049242A (en) 1997-10-14 2000-04-11 Cypress Semiconductor Corp. Voltage reference source for an overvoltage-tolerant bus interface
US6496054B1 (en) 2000-05-13 2002-12-17 Cypress Semiconductor Corp. Control signal generator for an overvoltage-tolerant interface circuit on a low voltage process
US8018268B1 (en) 2004-11-19 2011-09-13 Cypress Semiconductor Corporation Over-voltage tolerant input circuit
JP2007246117A (ja) * 2006-03-15 2007-09-27 Dainippon Ink & Chem Inc 内蓋付きタンク

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3796998A (en) * 1971-09-07 1974-03-12 Texas Instruments Inc Mos dynamic memory
US3921011A (en) * 1974-06-03 1975-11-18 Motorola Inc MOS input latch circuit
US4172282A (en) * 1976-10-29 1979-10-23 International Business Machines Corporation Processor controlled memory refresh
US4409501A (en) * 1981-07-20 1983-10-11 Motorola Inc. Power-on reset circuit
US4654826A (en) * 1984-08-20 1987-03-31 National Semiconductor Corporation Single device transfer static latch
FR2578125B1 (fr) * 1985-02-28 1987-04-10 Efcis Bascule bistable statique en technologie cmos
US4698526A (en) * 1985-10-17 1987-10-06 Inmos Corporation Source follower CMOS input buffer

Also Published As

Publication number Publication date
JPH0817028B2 (ja) 1996-02-21
EP0226929A2 (de) 1987-07-01
DE3688049T2 (de) 1993-09-09
EP0226929B1 (de) 1993-03-17
EP0226929A3 (en) 1989-04-26
US4825415A (en) 1989-04-25
JPS62134897A (ja) 1987-06-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee