DE3681698D1 - Saat- und stichverfahren zu integrierten feldanordnungen. - Google Patents

Saat- und stichverfahren zu integrierten feldanordnungen.

Info

Publication number
DE3681698D1
DE3681698D1 DE8686115608T DE3681698T DE3681698D1 DE 3681698 D1 DE3681698 D1 DE 3681698D1 DE 8686115608 T DE8686115608 T DE 8686115608T DE 3681698 T DE3681698 T DE 3681698T DE 3681698 D1 DE3681698 D1 DE 3681698D1
Authority
DE
Germany
Prior art keywords
titching
seeding
procedures
integrated field
field arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686115608T
Other languages
English (en)
Inventor
Raymond John Ferreri
Douglas Bingham Fields
Walter Rudolf Heitmueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3681698D1 publication Critical patent/DE3681698D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8686115608T 1985-12-09 1986-11-11 Saat- und stichverfahren zu integrierten feldanordnungen. Expired - Fee Related DE3681698D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/806,650 US4775942A (en) 1985-12-09 1985-12-09 Seed and stitch approach to embedded arrays

Publications (1)

Publication Number Publication Date
DE3681698D1 true DE3681698D1 (de) 1991-10-31

Family

ID=25194518

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686115608T Expired - Fee Related DE3681698D1 (de) 1985-12-09 1986-11-11 Saat- und stichverfahren zu integrierten feldanordnungen.

Country Status (4)

Country Link
US (1) US4775942A (de)
EP (1) EP0225499B1 (de)
JP (1) JPH0744257B2 (de)
DE (1) DE3681698D1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282475B1 (de) * 1986-08-11 1991-12-18 Koninklijke Philips Electronics N.V. Integrierter halbleiterspeicher und integrierter signalprozessor mit solchem speicher
US5089973A (en) * 1986-11-07 1992-02-18 Apple Computer Inc. Programmable logic cell and array
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
US5224057A (en) * 1989-02-28 1993-06-29 Kabushiki Kaisha Toshiba Arrangement method for logic cells in semiconductor IC device
US5644496A (en) * 1989-08-15 1997-07-01 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5260881A (en) * 1989-10-30 1993-11-09 Advanced Micro Devices, Inc. Programmable gate array with improved configurable logic block
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5422857A (en) * 1989-11-21 1995-06-06 Matsushita Electric Industrial Co., Ltd. Semiconductor memory unit having overlapping addresses
JP2575564B2 (ja) * 1991-03-05 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 自動マクロ最適順序化方法
GB2280293B (en) * 1993-07-19 1997-12-10 Hewlett Packard Co Architecture for programmable logic
US5818726A (en) * 1994-04-18 1998-10-06 Cadence Design Systems, Inc. System and method for determining acceptable logic cell locations and generating a legal location structure
US5802003A (en) * 1995-12-20 1998-09-01 International Business Machines Corporation System for implementing write, initialization, and reset in a memory array using a single cell write port
US5914906A (en) 1995-12-20 1999-06-22 International Business Machines Corporation Field programmable memory array
US6570404B1 (en) 1996-03-29 2003-05-27 Altera Corporation High-performance programmable logic architecture
US5689514A (en) * 1996-09-30 1997-11-18 International Business Machines Corporation Method and apparatus for testing the address system of a memory system
US5826006A (en) * 1996-09-30 1998-10-20 International Business Machines Corporation Method and apparatus for testing the data output system of a memory system
US6289494B1 (en) 1997-11-12 2001-09-11 Quickturn Design Systems, Inc. Optimized emulation and prototyping architecture
KR100254564B1 (ko) * 1997-12-20 2000-05-01 윤종용 반도체 장치
US6373122B1 (en) * 1999-04-12 2002-04-16 Tanner Research, Inc. Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array
AU5127600A (en) * 1999-05-07 2000-11-21 Morphics Technology, Inc. Heterogeneous programmable gate array
US6697957B1 (en) 2000-05-11 2004-02-24 Quickturn Design Systems, Inc. Emulation circuit with a hold time algorithm, logic analyzer and shadow memory
US6557149B2 (en) * 2001-04-04 2003-04-29 Intel Corporation Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate
US7212961B2 (en) * 2002-08-30 2007-05-01 Lsi Logic Corporation Interface for rapid prototyping system
US7299427B2 (en) * 2002-08-30 2007-11-20 Lsi Corporation Radio prototyping system
US8514634B1 (en) * 2011-09-20 2013-08-20 Xilinx, Inc. Multi-protocol gearbox

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US101804A (en) * 1870-04-12 Improved wooden box
DE2739952C2 (de) * 1977-09-05 1983-10-13 Computer Gesellschaft Konstanz Mbh, 7750 Konstanz Großintegrierter Halbleiter-Speicherbaustein in Form einer unzerteilten Halbleiterscheibe
US4233674A (en) * 1978-08-07 1980-11-11 Signetics Corporation Method of configuring an integrated circuit
JPS5766587A (en) * 1980-10-09 1982-04-22 Fujitsu Ltd Static semiconductor storage device
JPS58119076A (ja) * 1982-01-08 1983-07-15 Toshiba Corp 画像編集装置
US4584653A (en) * 1983-03-22 1986-04-22 Fujitsu Limited Method for manufacturing a gate array integrated circuit device
US4627015A (en) * 1983-05-31 1986-12-02 International Business Machines Corp. Text placement on graphics screen
US4612618A (en) * 1983-06-10 1986-09-16 Rca Corporation Hierarchical, computerized design of integrated circuits
JPS6047441A (ja) * 1983-08-26 1985-03-14 Fujitsu Ltd 半導体集積回路
US4688072A (en) * 1984-06-29 1987-08-18 Hughes Aircraft Company Hierarchical configurable gate array
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells
US4613941A (en) * 1985-07-02 1986-09-23 The United States Of America As Represented By The Secretary Of The Army Routing method in computer aided customization of a two level automated universal array

Also Published As

Publication number Publication date
JPS62137842A (ja) 1987-06-20
EP0225499A2 (de) 1987-06-16
JPH0744257B2 (ja) 1995-05-15
EP0225499B1 (de) 1991-09-25
EP0225499A3 (en) 1988-06-22
US4775942A (en) 1988-10-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee