DE3670402D1 - Senkrecht isolierte komplementaere transistorstrukturen. - Google Patents

Senkrecht isolierte komplementaere transistorstrukturen.

Info

Publication number
DE3670402D1
DE3670402D1 DE8686100564T DE3670402T DE3670402D1 DE 3670402 D1 DE3670402 D1 DE 3670402D1 DE 8686100564 T DE8686100564 T DE 8686100564T DE 3670402 T DE3670402 T DE 3670402T DE 3670402 D1 DE3670402 D1 DE 3670402D1
Authority
DE
Germany
Prior art keywords
transistor structures
complementary transistor
vertical insulated
insulated
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686100564T
Other languages
English (en)
Inventor
John Robert Abernathey
Iii Charles William Koburger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3670402D1 publication Critical patent/DE3670402D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8686100564T 1985-01-28 1986-01-17 Senkrecht isolierte komplementaere transistorstrukturen. Expired - Fee Related DE3670402D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/695,716 US4556585A (en) 1985-01-28 1985-01-28 Vertically isolated complementary transistors

Publications (1)

Publication Number Publication Date
DE3670402D1 true DE3670402D1 (de) 1990-05-17

Family

ID=24794198

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686100564T Expired - Fee Related DE3670402D1 (de) 1985-01-28 1986-01-17 Senkrecht isolierte komplementaere transistorstrukturen.

Country Status (5)

Country Link
US (1) US4556585A (de)
EP (1) EP0190581B1 (de)
JP (1) JPS61177770A (de)
CA (1) CA1208805A (de)
DE (1) DE3670402D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4728624A (en) * 1985-10-31 1988-03-01 International Business Machines Corporation Selective epitaxial growth structure and isolation
US4729006A (en) * 1986-03-17 1988-03-01 International Business Machines Corporation Sidewall spacers for CMOS circuit stress relief/isolation and method for making
US4891247A (en) * 1986-09-15 1990-01-02 Watkins-Johnson Company Process for borosilicate glass films for multilevel metallization structures in semiconductor devices
KR880005690A (ko) * 1986-10-06 1988-06-30 넬손 스톤 선택적인 에피켁샬층을 사용한 BiCMOS 제조방법
DE3700102A1 (de) * 1987-01-03 1988-07-14 Kallabis Manfred Schaft einer gelenk-endoprothese
US4902641A (en) * 1987-07-31 1990-02-20 Motorola, Inc. Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure
US4876212A (en) * 1987-10-01 1989-10-24 Motorola Inc. Process for fabricating complimentary semiconductor devices having pedestal structures
US4820654A (en) * 1987-12-09 1989-04-11 Ncr Corporation Isolation of regions in a CMOS structure using selective epitaxial growth
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
DE3841763A1 (de) * 1988-12-12 1990-06-13 Basf Ag Neue tnf-peptide
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures
DE4300986C2 (de) * 1992-01-17 1999-08-26 Mitsubishi Electric Corp Halbleitervorrichtung zur Elementisolierung und Herstellungsverfahren derselben
US5821172A (en) * 1997-01-06 1998-10-13 Advanced Micro Devices, Inc. Oxynitride GTE dielectrics using NH3 gas
KR20130054010A (ko) * 2011-11-16 2013-05-24 삼성전자주식회사 Ｉｉｉ-ｖ족 물질을 이용한 반도체 소자 및 그 제조방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137109A (en) * 1976-04-12 1979-01-30 Texas Instruments Incorporated Selective diffusion and etching method for isolation of integrated logic circuit
JPS55160443A (en) * 1979-05-22 1980-12-13 Semiconductor Res Found Manufacture of semiconductor integrated circuit device
US4309716A (en) * 1979-10-22 1982-01-05 International Business Machines Corporation Bipolar dynamic memory cell
US4476623A (en) * 1979-10-22 1984-10-16 International Business Machines Corporation Method of fabricating a bipolar dynamic memory cell
JPS58192346A (ja) * 1982-05-06 1983-11-09 Toshiba Corp 半導体装置の製造方法
JPS58197871A (ja) * 1982-05-14 1983-11-17 Toshiba Corp 半導体装置およびその製造方法
JPS5919347A (ja) * 1982-07-23 1984-01-31 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法

Also Published As

Publication number Publication date
CA1208805A (en) 1986-07-29
US4556585A (en) 1985-12-03
EP0190581B1 (de) 1990-04-11
EP0190581A2 (de) 1986-08-13
EP0190581A3 (en) 1987-08-19
JPS61177770A (ja) 1986-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee