DE3650165T2 - Bus state control circuit. - Google Patents

Description

The invention relates to a bus state control circuit of a microprocessor, and more particularly to a bus state control circuit provided within a microprocessor to which an input-output control (peripheral control) IC is coupled through a bus.

Access by a microprocessor to an input-output control IC such as a communication control IC and a magnetic disk control IC has heretofore been performed by executing input-output instructions. Normally, even if the same input-output control IC is accessed consecutively according to predetermined instructions, there is no problem with the "recovery time" of the input-output control IC, i.e., the time period between the end of one access and the start of a subsequent access, because the operating frequency of the microprocessor is small and an instruction fetch operation for finding the next instruction always occurs between input-output accesses.

Fig. 1 is a timing diagram relating to external access in the case where a microprocessor executes consecutive input-output instructions in a known manner. A key signal DS is used to read and write data, and it indicates the time when access is possible. The "recovery time" is considered to be the time period between the time when the key signal becomes inactive and the time when it is again available for access to the new input-output control IC. becomes active. As shown in Fig. 1, a long recovery time is obtained even when the same input-output control IC is accessed consecutively because the instruction fetch cycle is inserted between the consecutive input-output access cycles.

Together with improvements in the integration capacity of LSI, the capabilities and functions of microprocessors are in some places approaching those of microcomputers and medium-sized general-purpose computers. Improvements in microelement manufacturing techniques and the introduction of a pipeline structure in the microprocessor architecture have contributed to this progress.

With the improvement of microprocessor architecture, the external access ratio, i.e., the so-called "bus access ratio", has been raised to a very substantial level. In other words, processes such as instruction fetch, instruction decoding, operand access and instruction execution, which were previously performed serially, can now be performed in parallel due to the pipeline structure of the microprocessor architecture. By the same measure as operand access, reading an operand required for an instruction subsequent to a given instruction that is currently being executed and writing an operand contained in an instruction that has already been completed are required sequentially.

Regarding the input and output operations, these are performed successively for the same input-output control IC, and the input-output access cycles may sometimes occur consecutively without inserting the instruction fetch cycle. This causes a problem in that the recovery time cannot be ensured because the The time period between the end of one access and the beginning of a subsequent access becomes short.

A system in which software is prepared such that input-output instructions are not executed consecutively is one way of solving the above problem. However, such a system must take into account factors related to hardware, such as the pipeline structure of a given microprocessor, the degree of parallel execution of instructions, the clock frequency and the recovery time for the input-output IC. Consequently, a significant burden is imposed on a software developer. Furthermore, even if a program solution is implemented, the same program cannot work in another system having different factors related to hardware. Even if the software allows sufficient time between input-output instructions so that it can work in different systems, it will operate such inefficient systems which do not require so much time for recovery.

As described above, there are several disadvantages in the system where the recovery time is ensured by software.

Another solution can be found in a system where hardware provides a fixed amount of time to ensure recovery time that is always inserted between input and output accesses. This system has a disadvantage in that an unnecessary amount of time is consumed when input and output accesses are not performed consecutively to the same IC. This leads to a limitation in terms of system performance.

E.D.N. Electrical Design News, Volume 30, No. 7, April 1985, pages 274-275, Boston, Mass., United States of America; I.R. JOHNS: "Interface circuittry tames Z8530", describes a monostable timer for ensuring the minimum time between successive bus accesses from a CPU to an I/O device. This means that the timer described in this publication is an interface circuit and a bus state control circuit is not disclosed.

An object of the invention is to provide a bus state control circuit capable of ensuring the recovery time of the input-output control IC.

Another object of the invention is to provide a bus state control circuit that can be operated without considering the hardware such as pipeline structure, the degree of parallel execution of instructions, clock frequency and recovery time of the input-output control IC.

Another object of the invention is to provide a bus state control circuit capable of reducing the burden of a software developer.

Another object of the invention is to provide a bus state control circuit that operates effectively even when constructed with different hardware elements.

Yet another object of the invention is to provide a bus state control circuit that is effectively operable even when access to the input-output control IC is not continuous.

These objects are achieved by a bus state control circuit as defined in the claim.

Other objects and features of the invention will become apparent from the following description with reference to the drawings.

Fig. 1 is a timing diagram for a bus for the case where a sequentially processing microprocessor issues consecutive input-output commands according to a known circuit,

Fig. 2 is a circuit diagram of an embodiment of a bus state control circuit according to the invention;

Fig. 3 is a state transition diagram of the embodiment according to Fig. 2,

Fig. 4 is a circuit diagram of a clock signal generating circuit and

Fig. 5 to 8 are timing diagrams of the embodiment of Fig. 2.

Preferred embodiment of the invention

Fig. 2 shows a structure of an embodiment (two-phase clock system) of the bus state control circuit according to the invention.

D-flip-flops 102 to 107 receive a first clock signal PHI1 and generate respective output signals PI, T1, T2, T3 and TR which indicate the current bus state. The outputs TI, T1, T2, T3 and TR indicate a sleep state, a first state, a second state, a third state and a state for ensuring a recovery time, respectively. D-flip-flops 108 to 112 receive a second clock signal PHI2 and are provided for delaying the current states TI, T1, T2, T3 and TR. D-flip-flops 114 and 115 provide a signal PIOAC which is obtained by delaying an I/O access signal IOAC by one clock period. A combinational logic circuit 201 receives as inputs the output signals TI, T1, T2, T3 and TR of the current bus state. It also receives an access request signal ACREQ indicating a request for access, an I/O access signal IOAC indicating that the access request signal ACREQ relates to a specific input-output when this signal is active, the signal PIOAC obtained by delaying the I/O access signal IQAC by one clock pulse, and a wait signal WAIT requesting an extension of an access cycle. The access request signal ACREQ is generated during a predetermined period of time when a central processing unit (CPU) of a microprocessor requires access to an external element such as an external main memory or a peripheral unit. For example, this ACREQ signal is generated by an instruction decoder when the decoder decodes an instruction for external access (e.g., memory read, memory write, I/O read, I/O write).

The I/O access signal IOAC becomes active when the input-output control unit is to be accessed. This IOAC signal can also be generated by the command decoder.

The wait signal WAIT becomes active when a long access time is required. In this embodiment, when an access time longer than the time T1 to T3 is required, the WAIT signal becomes active for a desired time. For example, in a case that a low-speed memory or a low-speed peripheral device is accessed, the WAIT signal becomes active.

The logic circuit 101 determines a subsequent bus state.

The following Table 1 is a truth table of the combinational logic circuit 101. Table 1 Input Output Delayed signals

The operation of the present embodiment will now be explained with reference to Table 1.

First, assume that the current bus state is state TI (S1). When the access request signal ACREQ becomes active, a transition to state T1 (S2) is made. Next, a transition to state T2 (S3) is made. If the wait signal WAIT is active in state T2, state T2 remains (S4), if this signal is inactive, a transition to state T3 is made (S5). This process is used to ensure a Access time for the input-output control IC is performed. If the access request signal ACREQ is inactive in state T3, a transition to state TI is performed (S9). After state T3 (S5), if the access request signal ACREQ is active and if the I/O access signal IOAC is inactive, a transition to state T1 is performed (S6). In this embodiment, in S6, the input-output control unit is not accessed while an external memory is being accessed. If the access request signal ACREQ is active and the I/O access signal IOAC is active, a transition to state T1 is performed after state T3, without state TR, if PIOAC is inactive (S7). That is, if the previous access is not an I/O access, state T3 is changed directly to state T1 without recovery time. On the other hand, if the ACREQ signal is active and the PIOAC is also active, a transition to the TR state is made from the T3 state if the IQAC is active (S8). That is, if the IOAC signals are activated consecutively at least twice, the TR state is necessarily inserted between the T3 and T1 states. In this way, the recovery time is created. A transition from the TR state to the T1 state is necessarily made (S10).

Fig. 3 is a state transition diagram of the process described above.

As shown in Table 1, the state TR is generated only when the I/O access is required consecutively. The duration of the state T3 can be determined in advance according to the recovery time of the input-output control unit. In this embodiment, one clock period is assigned to the state TR. The state TR is omitted when the previous access is not an IO access. Furthermore, the state TR can be omitted. if a duration longer than the recovery time occurs between consecutive I/O accesses because the D flip-flop 115 is reset.

An actual key signal is generated using the state T1 and the state T3 as shown in Fig. 4. Each of the D flip-flops 103, 105, 106 and 107 outputs a pulse signal. Each pulse signal is active in one cycle of the clock signal PHI1. The states T1, T2, T3 and TR are represented by output pulse signals of the flip-flops 103, 105, 106 and 107, respectively.

In Fig. 4, the output pulse signal indicating the state T1, that is the pulse signal from the flip-flop 103, is fed to an AND gate 120, while the output pulse signal (T3) from the flip-flop 106 is fed to an AND gate 121. These two AND signals are controlled by the clock signal PHI 2. The output of the AND gate 120 is connected to a set terminal (S) of a set-reset flip-flop 122. The output of the AND gate 121 is connected to a reset terminal (R) of the flip-flop 122. The flip-flop 122 activates a key signal (DS) when both the signal (T1) and the signal PHI2 are received from the AND gate 120, and inactivates the key signal (DS) when the signal (T3) and PHI2 are received from the AND gate 121. Thus, the key signal DS is generated from the input timing of the signal (T1) to the input timing of the signal (T3).

In this embodiment of the invention, the key signal is activated in states T1, T2 and T3 when the PIOAC signal is inactive. The key signal is activated in states T1, T2, T3 and TR when the PIQAC signal is activated because the reset time of the flip-flop 122 is delayed by inserting the state TR (recovery time).

Fig. 5 is a timing diagram for the case where a memory access is performed subsequent to an output-input access. The diagram shows the transition from the state T3 in which a memory access cycle is performed to the state T1 of the input-output access cycle. Fig. 6 is a timing diagram for the case where an input-output access is performed subsequent to the memory access. The transition is performed from the state T3 of the input-output access cycle to the state T1 of the memory access cycle. Fig. 7 is a timing diagram for the case where the input-output access is performed sequentially. The diagram shows that a transition is made once from the state T4 of the initial input-output access cycle to the state TR to ensure the recovery time before the transition to the state T1 of the following input-output access cycle. Fig. 8 is a timing diagram for the case where input-output access cycles are performed consecutively with the state T1 interposed. It is shown that in this case the recovery time is ensured without passing through the state TR.

In the embodiment described above, a one-clock interval is assigned to the recovery time ensuring state. It may happen that the one-clock interval is not sufficient to ensure the recovery time of the input-output control IC due to such factors as the clock frequency of a microprocessor and the number of clocks for one bus access cycle. In this case, the recovery time can be ensured in a simple manner by structuring the bus state control circuit such that the recovery time ensuring state is increased as required and that, when an input-output access cycle is consecutive, a subsequent input-output cycle is started after which the thus increased state has passed through. The logic circuit 101 can be modified to extend the state TR in accordance with the required recovery time. For example, a delay gate for delaying the transition from the state TR to the state T1 is introduced into the logic circuit 101. The logic circuit 101 can be formed by a known arbitrary logic circuit.

As described above, with the present invention, the recovery time of an input-output control IC can be ensured with only an inevitable minimum deterioration in the performance of a microprocessor merely by delaying the start of a subsequent bus cycle when the bus cycles for input and output are consecutive. The invention uses a system in which a first signal indicating that an access request signal is for an input-output device and a second signal indicating that an access was immediately before the signal for the input-output device are input together into a bus state sequence. Furthermore, a state for ensuring the recovery time is inserted only in the case where a previous access to the input-output device has been made and accesses for the input-output device are made consecutively.

Further, according to the present invention, the key signal may be used as an I/O read key signal or an I/O write key signal. When a memory requiring the recovery time is used, the present invention is also applied there. In this case, the inverted IOAC signal may be input to the flip-flop 114. A memory access signal may be used as the IOAC signal.

Claims (1)

1. Bus state control circuit in a microprocessor system to be connected to an input-output device, the bus state control circuit responsive to a first clock signal (PHI1), an access request signal (ACREQ), a second clock signal (PHI2) and to input-output device access signals (IQAC, PiOAC), the bus state control circuit comprising: a key signal generating circuit (120, 121, 122) which generates a key signal (DS) which is supplied to the input-output device for indicating the time at which access to the input-output is possible, a first delay device (102-107) which outputs a number of bus status signals (T1-T3 and TR) in dependence on the first clock signal (PHI1), a second delay device (108-113) connected to the first delay device (102-107) for generating a number of second delay signals corresponding to the output of the first delay device (102-107) in dependence on the second clock signal (PHI2), a third delay means (114, 115) responsive to the device access signal (IOAC) for generating a third delay signal (PIOAC) for a clock period and logic means (101) connected to said first delay means (102-107) and responsive to the outputs of said second delay means (108-113) and further responsive to said access request signal (ACRIQ) and said input-output device access signal (IOAC) and said third delay signal (PIOAC) for determining the next bus states and for supplying signals indicative of such states to the first delay means (102-107), the key signal generating circuit (120, 121, 122) being responsive to: a first bus status signal (T1) for controlling the start-time control of the key signal (DS), a second bus status signal (T3) for controlling the end time of the key signal (DS) and a third bus state signal (TR) for delaying the start of the start for a predetermined period of time in the event that a previous access to the input-output device has taken place, the third bus state signal (TR) only becoming active when both the access request signal (ACRIQ), the delayed I/O access signal (PIDAC) and the I/O access signal (IOAC) are active and the key signal generating circuit (120, 121, 122) starts the access directly in the case when a previous access to a device other than the input-output device has been carried out or when the previous access to the input-output device has taken place but a predetermined period of time has elapsed when the access request signal indicates access to the input-output device.