DE3587882D1 - Speichereinheit mit arithmetischen und logischen Funktionen, insbesondere für graphische Datenverarbeitung. - Google Patents

Speichereinheit mit arithmetischen und logischen Funktionen, insbesondere für graphische Datenverarbeitung.

Info

Publication number
DE3587882D1
DE3587882D1 DE3587882T DE3587882T DE3587882D1 DE 3587882 D1 DE3587882 D1 DE 3587882D1 DE 3587882 T DE3587882 T DE 3587882T DE 3587882 T DE3587882 T DE 3587882T DE 3587882 D1 DE3587882 D1 DE 3587882D1
Authority
DE
Germany
Prior art keywords
arithmetic
storage unit
data processing
graphic data
logical functions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3587882T
Other languages
English (en)
Other versions
DE3587882T2 (de
Inventor
Koichi Kimura
Toshihiko Ogura
Hiroaki Aotsu
Mitsuru Ikegami
Tadashi Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP10585084A external-priority patent/JPS60251319A/ja
Priority claimed from JP59208266A external-priority patent/JPS6187194A/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3587882D1 publication Critical patent/DE3587882D1/de
Publication of DE3587882T2 publication Critical patent/DE3587882T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Image Processing (AREA)
DE19853587882 1984-05-20 1985-10-02 Speichereinheit mit arithmetischen und logischen Funktionen, insbesondere für graphische Datenverarbeitung. Expired - Fee Related DE3587882T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10585084A JPS60251319A (ja) 1984-05-20 1984-05-25 加熱装置
JP59208266A JPS6187194A (ja) 1984-10-05 1984-10-05 記憶回路

Publications (2)

Publication Number Publication Date
DE3587882D1 true DE3587882D1 (de) 1994-08-18
DE3587882T2 DE3587882T2 (de) 1994-11-24

Family

ID=26446078

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853587882 Expired - Fee Related DE3587882T2 (de) 1984-05-20 1985-10-02 Speichereinheit mit arithmetischen und logischen Funktionen, insbesondere für graphische Datenverarbeitung.

Country Status (2)

Country Link
EP (1) EP0189524B1 (de)
DE (1) DE3587882T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63163888A (ja) * 1986-12-26 1988-07-07 ミノルタ株式会社 メモリの読み書き制御回路
US4918526A (en) * 1987-03-20 1990-04-17 Digital Equipment Corporation Apparatus and method for video signal image processing under control of a data processing system
US5023838A (en) * 1988-12-02 1991-06-11 Ncr Corporation Random access memory device with integral logic capability
JP3075184B2 (ja) * 1996-08-02 2000-08-07 日本電気株式会社 演算処理機能付主記憶システム及びその制御方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3984670A (en) * 1975-03-26 1976-10-05 Fairchild Camera And Instrument Corporation Expandable digital arithmetic logic register stack
US3976982A (en) * 1975-05-12 1976-08-24 International Business Machines Corporation Apparatus for image manipulation
FR2509892B1 (fr) * 1981-07-16 1986-05-09 Ampex Memoire de donnees a complementation selective et procede d'utilisation d'une telle memoire
JPS58115673A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 記憶情報制御方式及び装置
JPS58125281A (ja) * 1982-01-19 1983-07-26 Fujitsu Ltd 記憶装置

Also Published As

Publication number Publication date
EP0189524A3 (en) 1987-05-27
DE3587882T2 (de) 1994-11-24
EP0189524A2 (de) 1986-08-06
EP0189524B1 (de) 1994-07-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee