DE3585827D1 - System zur steuerung einer aenderung der reihenfolge von kanaldaten. - Google Patents

System zur steuerung einer aenderung der reihenfolge von kanaldaten.

Info

Publication number
DE3585827D1
DE3585827D1 DE8585116619T DE3585827T DE3585827D1 DE 3585827 D1 DE3585827 D1 DE 3585827D1 DE 8585116619 T DE8585116619 T DE 8585116619T DE 3585827 T DE3585827 T DE 3585827T DE 3585827 D1 DE3585827 D1 DE 3585827D1
Authority
DE
Germany
Prior art keywords
channel data
data order
controlling change
controlling
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE8585116619T
Other languages
English (en)
Inventor
Toru Kosugi
Katsutoshi Miyaji
Kouichi Sugama
Tamio Oonuma
Minoru Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26551443&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3585827(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from JP27829084A external-priority patent/JPS61156932A/ja
Priority claimed from JP27538184A external-priority patent/JPS61157037A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3585827D1 publication Critical patent/DE3585827D1/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1641—Hierarchical systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
DE8585116619T 1984-12-27 1985-12-27 System zur steuerung einer aenderung der reihenfolge von kanaldaten. Revoked DE3585827D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP27829084A JPS61156932A (ja) 1984-12-27 1984-12-27 チヤンネルデ−タ並び換え制御方式
JP27538184A JPS61157037A (ja) 1984-12-28 1984-12-28 複数シリアルデ−タ間のワ−ド乗換方式

Publications (1)

Publication Number Publication Date
DE3585827D1 true DE3585827D1 (de) 1992-05-14

Family

ID=26551443

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116619T Revoked DE3585827D1 (de) 1984-12-27 1985-12-27 System zur steuerung einer aenderung der reihenfolge von kanaldaten.

Country Status (4)

Country Link
US (1) US4740959A (de)
EP (1) EP0186912B1 (de)
CA (1) CA1255018A (de)
DE (1) DE3585827D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1292333C (en) * 1987-05-15 1991-11-19 Masayoshi Shimada Digital time division multiplex systems and method of controlling same
US4933930A (en) * 1988-10-31 1990-06-12 International Business Machines Corporation High speed switch as for an optical communication system
JP3060507B2 (ja) * 1990-09-11 2000-07-10 ソニー株式会社 ディジタル信号伝送装置
JP2888004B2 (ja) * 1992-01-24 1999-05-10 日本電気株式会社 伝送回線インタフェース回路
US6253247B1 (en) * 1996-11-21 2001-06-26 Ragula Systems System and method for transmitting a user's data packets concurrently over different telephone lines between two computer networks
JPH10247881A (ja) * 1997-03-04 1998-09-14 Hitachi Telecom Technol Ltd 時分割多重化装置
US5938763A (en) * 1997-08-06 1999-08-17 Zenith Electronics Corporation System for transposing data from column order to row order

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5026245B1 (de) * 1970-06-29 1975-08-29
SU661831A1 (ru) * 1977-03-28 1979-05-05 Предприятие П/Я В-2655 Многоканальное устройство дл передачи данных
US4204093A (en) * 1978-05-19 1980-05-20 Bell Telephone Laboratories, Incorporated Variable frame rate technique for use in a time-division multiple access (TDMA) communication system
US4298977A (en) * 1979-09-10 1981-11-03 Bell Telephone Laboratories, Incorporated Broadcast and alternate message time slot interchanger
DE3045606C2 (de) * 1980-12-03 1984-04-05 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung für Zeitmultiplex-Fernmeldevermittlungsanlagen für Mehrkanalverbindungen
US4475188A (en) * 1982-09-02 1984-10-02 Burroughs Corp. Four way arbiter switch for a five port module as a node in an asynchronous speed independent network of concurrent processors
US4545053A (en) * 1984-03-21 1985-10-01 At&T Information Systems Inc. Time slot interchanger

Also Published As

Publication number Publication date
EP0186912B1 (de) 1992-04-08
US4740959A (en) 1988-04-26
EP0186912A2 (de) 1986-07-09
CA1255018A (en) 1989-05-30
EP0186912A3 (en) 1988-09-28

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8339 Ceased/non-payment of the annual fee
8331 Complete revocation
8380 Miscellaneous part iii

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