DE3579794D1 - Arbiterschaltung. - Google Patents

Arbiterschaltung.

Info

Publication number
DE3579794D1
DE3579794D1 DE8585116191T DE3579794T DE3579794D1 DE 3579794 D1 DE3579794 D1 DE 3579794D1 DE 8585116191 T DE8585116191 T DE 8585116191T DE 3579794 T DE3579794 T DE 3579794T DE 3579794 D1 DE3579794 D1 DE 3579794D1
Authority
DE
Germany
Prior art keywords
arbiterschaltung
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585116191T
Other languages
English (en)
Inventor
William Jack Pantry
Burke Brian Baumann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of DE3579794D1 publication Critical patent/DE3579794D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Lock And Its Accessories (AREA)
  • Electronic Switches (AREA)
  • Circuits Of Receivers In General (AREA)
DE8585116191T 1984-12-20 1985-12-18 Arbiterschaltung. Expired - Fee Related DE3579794D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/684,312 US4612542A (en) 1984-12-20 1984-12-20 Apparatus for arbitrating between a plurality of requestor elements

Publications (1)

Publication Number Publication Date
DE3579794D1 true DE3579794D1 (en) 1990-10-25

Family

ID=24747555

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116191T Expired - Fee Related DE3579794D1 (en) 1984-12-20 1985-12-18 Arbiterschaltung.

Country Status (9)

Country Link
US (1) US4612542A (de)
EP (1) EP0185370B1 (de)
JP (1) JPH0690701B2 (de)
AU (1) AU584138B2 (de)
CA (1) CA1244109A (de)
DE (1) DE3579794D1 (de)
NO (1) NO170867C (de)
SG (1) SG94590G (de)
ZA (1) ZA859383B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6275860A (ja) * 1985-09-30 1987-04-07 Toshiba Corp デ−タ転送制御装置
AU586120B2 (en) * 1986-09-02 1989-06-29 Amdahl Corporation A method and apparatus for arbitration and serialization in a multiprocessor system
JPH073940B2 (ja) * 1987-11-19 1995-01-18 三菱電機株式会社 アービタ回路
JPH01134557A (ja) * 1987-11-19 1989-05-26 Mitsubishi Electric Corp アービタ回路
JPH01147647A (ja) * 1987-12-03 1989-06-09 Mitsubishi Electric Corp データ処理装置
US4872004A (en) * 1988-05-02 1989-10-03 Sun Electric Corporation Plural source arbitration system
US4940908A (en) * 1989-04-27 1990-07-10 Advanced Micro Devices, Inc. Method and apparatus for reducing critical speed path delays
EP0464237A1 (de) * 1990-07-03 1992-01-08 International Business Machines Corporation Busarbitrierungsschema
WO1992015060A1 (en) * 1991-02-19 1992-09-03 International Business Machines Corporation Channel selection arbitration
US5341052A (en) * 1991-12-04 1994-08-23 North American Philips Corporation Arbiter with test capability and associated testing method
DE69224427T2 (de) * 1991-12-04 1998-08-13 Koninkl Philips Electronics Nv Arbiter mit einem unter Prioritätskonfliktskontrolle veränderlichen direkten Signal
JP2716911B2 (ja) * 1992-06-05 1998-02-18 三菱電機株式会社 優先順位選択回路
US5430848A (en) * 1992-08-14 1995-07-04 Loral Fairchild Corporation Distributed arbitration with programmable priorities
SE515316C2 (sv) * 1994-09-13 2001-07-16 Ericsson Telefon Ab L M Förfarande och anordning för att styra ett datanät
US5682467A (en) * 1994-09-29 1997-10-28 Xerox Corporation Arbitrating apparatus for controlling selective access of multiple bus masters to a printing system video bus
US5815023A (en) * 1997-03-20 1998-09-29 Sun Microsystems, Inc. Unbalanced multiplexer and arbiter combination

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603935A (en) * 1969-05-12 1971-09-07 Xerox Corp Memory port priority access system with inhibition of low priority lock-out
US4016539A (en) * 1973-09-12 1977-04-05 Nippon Electric Company, Ltd. Asynchronous arbiter
JPS53146550A (en) * 1977-05-27 1978-12-20 Nippon Telegr & Teleph Corp <Ntt> Conflict circuit
US4240138A (en) * 1978-10-03 1980-12-16 Texas Instruments Incorporated System for direct access to a memory associated with a microprocessor
JPS5922975B2 (ja) * 1978-11-13 1984-05-30 松下電器産業株式会社 信号優先順位決定回路
US4449183A (en) * 1979-07-09 1984-05-15 Digital Equipment Corporation Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
JPS56121126A (en) * 1980-02-26 1981-09-22 Toshiba Corp Priority level assigning circuit
US4423384A (en) * 1981-12-21 1983-12-27 Motorola, Inc. Asynchronous multi-port arbiter
US4472712A (en) * 1982-03-05 1984-09-18 At&T Bell Laboratories Multipoint data communication system with local arbitration
JPS58178454A (ja) * 1982-04-14 1983-10-19 Hitachi Ltd メモリ制御方式
JPS59161719A (ja) * 1983-03-07 1984-09-12 Hitachi Ltd バス占有制御装置
US4586128A (en) * 1983-04-14 1986-04-29 Burroughs Corporation Arbitrator circuit and technique for use in a digital computing system having multiple bus controllers

Also Published As

Publication number Publication date
EP0185370A1 (de) 1986-06-25
EP0185370B1 (de) 1990-09-19
CA1244109A (en) 1988-11-01
US4612542A (en) 1986-09-16
NO170867B (no) 1992-09-07
AU5047585A (en) 1986-06-26
NO170867C (no) 1992-12-16
NO854793L (no) 1986-06-23
JPH0690701B2 (ja) 1994-11-14
ZA859383B (en) 1986-08-27
SG94590G (en) 1991-01-18
AU584138B2 (en) 1989-05-18
JPS61151767A (ja) 1986-07-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee