DE3573965D1 - Semiconductor read only memory device and method of manufacturing the same - Google Patents

Semiconductor read only memory device and method of manufacturing the same

Info

Publication number
DE3573965D1
DE3573965D1 DE8585116126T DE3573965T DE3573965D1 DE 3573965 D1 DE3573965 D1 DE 3573965D1 DE 8585116126 T DE8585116126 T DE 8585116126T DE 3573965 T DE3573965 T DE 3573965T DE 3573965 D1 DE3573965 D1 DE 3573965D1
Authority
DE
Germany
Prior art keywords
manufacturing
same
memory device
semiconductor read
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585116126T
Other languages
English (en)
Inventor
Shoji Ariizumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3573965D1 publication Critical patent/DE3573965D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/34—Source electrode or drain electrode programmed

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE8585116126T 1984-12-25 1985-12-18 Semiconductor read only memory device and method of manufacturing the same Expired DE3573965D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59278410A JPS61150369A (ja) 1984-12-25 1984-12-25 読み出し専用半導体記憶装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE3573965D1 true DE3573965D1 (en) 1989-11-30

Family

ID=17596953

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116126T Expired DE3573965D1 (en) 1984-12-25 1985-12-18 Semiconductor read only memory device and method of manufacturing the same

Country Status (5)

Country Link
US (1) US4755864A (de)
EP (1) EP0186855B1 (de)
JP (1) JPS61150369A (de)
KR (1) KR900008940B1 (de)
DE (1) DE3573965D1 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789569B2 (ja) * 1986-03-26 1995-09-27 株式会社日立製作所 半導体集積回路装置及びその製造方法
US5293202A (en) * 1989-02-08 1994-03-08 Canon Kabushiki Kaisha Image fixing apparatus
US5606193A (en) * 1994-10-03 1997-02-25 Sharp Kabushiki Kaisha DRAM and MROM cells with similar structure
US6222216B1 (en) 1997-10-21 2001-04-24 Silicon Aquarius, Inc. Non-volatile and memory fabricated using a dynamic memory process and method therefor
US6433397B1 (en) * 2000-01-21 2002-08-13 International Business Machines Corporation N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
EP1202353A1 (de) 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Masken-programmiertes ROM und dessen Herstellungsverfahren
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
JP4729303B2 (ja) * 2002-05-14 2011-07-20 エイチアールエル ラボラトリーズ，エルエルシー リバースエンジニアリングに対する防御を有する集積回路
AU2003263748A1 (en) * 2002-06-21 2004-01-06 Micron Technology, Inc. Nrom memory cell, memory array, related devices and methods
US6853587B2 (en) * 2002-06-21 2005-02-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
JP4846239B2 (ja) 2002-12-13 2011-12-28 エイチアールエル ラボラトリーズ，エルエルシー ウェル注入を用いた集積回路の改変
JP2005024665A (ja) * 2003-06-30 2005-01-27 Ricoh Co Ltd 粉体搬送装置、画像形成装置、トナー収容部及びプロセスカートリッジ
US7095075B2 (en) * 2003-07-01 2006-08-22 Micron Technology, Inc. Apparatus and method for split transistor memory having improved endurance
US6979857B2 (en) 2003-07-01 2005-12-27 Micron Technology, Inc. Apparatus and method for split gate NROM memory
US6873550B2 (en) * 2003-08-07 2005-03-29 Micron Technology, Inc. Method for programming and erasing an NROM cell
US7085170B2 (en) 2003-08-07 2006-08-01 Micron Technology, Ind. Method for erasing an NROM cell
US6977412B2 (en) * 2003-09-05 2005-12-20 Micron Technology, Inc. Trench corner effect bidirectional flash memory cell
US6830963B1 (en) 2003-10-09 2004-12-14 Micron Technology, Inc. Fully depleted silicon-on-insulator CMOS logic
US7184315B2 (en) * 2003-11-04 2007-02-27 Micron Technology, Inc. NROM flash memory with self-aligned structural charge separation
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
US7301804B2 (en) * 2003-12-16 2007-11-27 Micro Technology, Inc. NROM memory cell, memory array, related devices and methods
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
US7157769B2 (en) * 2003-12-18 2007-01-02 Micron Technology, Inc. Flash memory having a high-permittivity tunnel dielectric
US6878991B1 (en) * 2004-01-30 2005-04-12 Micron Technology, Inc. Vertical device 4F2 EEPROM memory
US6952366B2 (en) * 2004-02-10 2005-10-04 Micron Technology, Inc. NROM flash memory cell with integrated DRAM
US7221018B2 (en) * 2004-02-10 2007-05-22 Micron Technology, Inc. NROM flash memory with a high-permittivity gate dielectric
US7075146B2 (en) * 2004-02-24 2006-07-11 Micron Technology, Inc. 4F2 EEPROM NROM memory arrays with vertical devices
US7072217B2 (en) * 2004-02-24 2006-07-04 Micron Technology, Inc. Multi-state memory cell with asymmetric charge trapping
US7102191B2 (en) * 2004-03-24 2006-09-05 Micron Technologies, Inc. Memory device with high dielectric constant gate dielectrics and metal floating gates
US7274068B2 (en) * 2004-05-06 2007-09-25 Micron Technology, Inc. Ballistic direct injection NROM cell on strained silicon structures
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4277881A (en) * 1978-05-26 1981-07-14 Rockwell International Corporation Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
JPS5626470A (en) * 1979-08-13 1981-03-14 Hitachi Ltd Field-effect transistor manufacturing process
US4305200A (en) * 1979-11-06 1981-12-15 Hewlett-Packard Company Method of forming self-registering source, drain, and gate contacts for FET transistor structures
US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
JPS56157056A (en) * 1980-05-09 1981-12-04 Fujitsu Ltd Manufacture of read-only memory
JPS5737857A (en) * 1980-08-20 1982-03-02 Fujitsu Ltd Manufacture of semiconductor device
EP0054102A3 (de) * 1980-12-11 1983-07-27 Rockwell International Corporation ROM-Zellen in sehr dichter Anordnung und Herstellungsverfahren
JPS59201461A (ja) * 1983-04-28 1984-11-15 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
JPS61150369A (ja) 1986-07-09
EP0186855A2 (de) 1986-07-09
EP0186855B1 (de) 1989-10-25
KR860005374A (ko) 1986-07-21
KR900008940B1 (ko) 1990-12-13
US4755864A (en) 1988-07-05
EP0186855A3 (en) 1986-10-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee