DE3541790C2 - Solid state light emitting diode array - Google Patents

Description

The invention relates to a light-emitting linear solid-state diode arrangement according to the preamble of the claim 1.

An arrangement according to the preamble of claim 1 is known known from document DE 26 08 562 A1. They are with her photosensitive areas designed to emit light parallel to the surface of the respective pn junction and thus emits parallel to the front of a semiconductor device Ren. To make this possible, the semiconductor device split. The runs parallel to this gap surface Etching channel, whose width decreases with increasing depth (forward MESA etching channel). The etch channels, the width of which increases with depth (reverse MESA etch channels) between adjacent light emitters regions extend from the gap surface extending beyond the forward MESA etch channel to that towards the side of the semiconductor device that corresponds to the gap area is opposite.

Furthermore, from JP 60-79783 (A) the structure of Kon clock electrodes known, which are in opposite transverse direction and a larger width in the wire bond area than in the contact area.

In addition, JP 57-138 354, JP 59-146874, JP 59-146875 and JP 59-15 9885 the following known.  

In Fig. 1, an electrostatic recording device is shown, which an exposure device A with a light-emitting diode arrangement 1 and a lens arrangement 2 for focusing the light emitted by the diode arrangement 1 , a developing device B for attaching toner particles to the electrostatic image on a Photosensitive drum 3 , a transfer corona device D for transferring the toner particles from the drum 3 to a recording paper that is transported in the direction of the arrow Z, a device E for removing an electrostatic potential on the drum 3 by appropriate exposure, a device F for Removal of remaining toner material from the drum 3 for cleaning the drum surface, a charging device G for charging the surface of the drum 3 to a uniform electrostatic potential, and a device H for fixing the transfer to the recording paper has a toner image by heating and pressurizing the toner image on the paper.

The exposure device A with the light-emitting diode arrangement 1 and the lens arrangement 2 is shown in more detail in FIG. 2. The lens arrangement 2 contains a plurality of rod-shaped lenses with self-focusing properties (so-called SELFOC lenses) for focusing the light 2 a, which is emitted by the light-emitting diode arrangement 1 .

In operation of the electrostatic recorder, the photosensitive drum 3 is rotated clockwise in Fig. 1. Her surface is charged evenly, in accordance with the discharge of the charging device G. The charged drum 3 is exposed with the aid of the light-emitting diode arrangement 1 , which is driven by corresponding recording signals, in order in this way an electrostatic image on the To produce surface of the drum 3 . This electrostatic image on the upper surface of the drum 3 is developed with the aid of toner particles which are deposited on the surface when the drum 3 moves clockwise past the developing device B. The surface of the drum 3 and the developing device B are in contact with each other. The toner image on the surface of the drum 3 is then transferred by means of the transfer corona device D to a recording or copying paper which moves in the direction of arrow Z in FIG. 1. The transmission takes place with the aid of an electrostatic field generated in the transmission corona device D. Then, the electrostatic image on the drum 3 is removed by exposure using the device E for removing the electrostatic potential on the drum 3 . Any remaining toner particles on the surface of the drum 3 are removed with the aid of the cleaning device F, which completes a recording cycle of the electrostatic recording device.

In FIGS. 3 to 5, a light emitting solid state diode array is shown how it can be used, for example, in the electrostatic recording apparatus. The light emitting diode arrangement comprises a substrate 10 made of n-type gallium arsenide (GaAs), an epitaxially grown layer 11 made of n-type GaAs _1-x P _x (x = crystal mixing ratio), a layer 12 made of n-type GaAs Recombination regions 13 of p-type, which are each formed through the surface of the n-type GaAs layer 12 and preferably by diffusion of Zn ge, insulation strips 14 which are produced in the same manner as the light-emitting recombination regions 13 and through which the respective light-emitting recombination regions 13 are isolated, separate electrodes 15 which lie on the respective light-emitting regions of the n-type GaAs layer 12 and to which a positive potential can be applied, and a common electrode 16 on the rear surface of the n- Type GaAs substrate 10 to which a negative potential can be applied. The n-type GaAs layer 12 and the respective electrodes 15 are provided with openings 17 in order to transmit or collect light which is emitted below the respective light-emitting recombination regions 13 .

In operation of the light-emitting diode array, electrons are injected from the n-type GaAs _1-x P _x layer 11 into the p-type light-emitting recombination regions 13 when a forward bias is applied between the respective positive electrodes 15 and the common negative electrode 16 is created. Light is then emitted outward in the direction of arrow L, namely through the opening 17 , which are both in the n-type GaAs layer 12 and in each of the electrodes 15 .

In the light-emitting diode arrangement described above, a uniform brightness is obtained in the area of the light-collecting openings 17 , as indicated by the solid line in FIG. 6. The positions x₁ to x₅ correspond to the positions or edge positions of the light-emitting recombination regions 13 , the openings 17 and the electrode 15 shown in FIG. 5. The uniform brightness is thus obtained between positions x₂ and x₃. This is because there is an at least approximately uniform electrical current flow in the area between the points x₁ to x₄, since the electrode 15 extends to the point x₄. The dashed lines in FIG. 6 mark the light energy generated in the light-emitting recombination region 13 .

The aforementioned light-emitting solid-state diode arrangement however, has the following disadvantages:

• (1) Even with a relatively large transition area between the pn layers, the amount of light emitted can only be increased to a certain extent by enlarging the openings 17 , since there is a risk that the electrodes 15 will break if the remaining edge of the electrodes is in the area the openings 17 is getting smaller and smaller.
• (2) In the manufacture of the light emitting diodes arrangement takes place a further step in the process Formation of a diffusion mask takes place because of Zn (zinc) to be diffused. The manufacturing process is therefore relatively complicated.
• (3) The cost of producing the light emitting diode arrays are also relative high because a considerable amount of Zn is consumed becomes.
• (4) The reject rate in the manufacture of the light  emitting diode arrays is relatively large because often diffusion of Zn in crystal defect areas he follows.
• (5) It is generally desirable that the light-emitting diode arrangement the positive potential to the common electrode and the negative potential applied to the individual or separate electrodes becomes. In this regard, the negative is disadvantageous Apply potential to the common electrode because no practically available donor diffusion source regarding the group of III-V semiconductor compounds is available so that only one n-type substrate can be used.
• (6) It is relatively difficult to be a light emitting Semiconductor arrangement of the type mentioned with very fine Structures if, on the other hand, these structures, for example the electrodes for the respective light emitting areas to be connected with wires have to.
• (7) The light generated in the light-emitting recombination region is, as indicated by the case Y in FIG. 5, partially emitted to the outside without penetrating through the openings 17 . As a result, the quality of the printed image or the image of a copy is reduced, which is produced with such a light-emitting diode arrangement, for example in an electrostatic recording device.

The invention has for its object a simple ago adjustable light-emitting solid-state diode arrangement with large light-emitting areas and with high efficiency to be specified in the generation of light.

The arrangement according to the invention is characterized by the features of Claim 1 given. It is characterized by a structure from, which makes it possible with simple measures ß, emitted towards the front of a semiconductor device rende pn areas to form, which over electrodes with large outer wire bond areas can be contacted.

It is particularly advantageous if the insulating layer on the front of the semiconductor arrangement made of PSG (Phos phor silicate glass).

The following is called the forward MESA etch channel designated, the width of which decreases with increasing depth; as a backward MESA etching channel one whose width increases with depth.  

According to an advantageous embodiment of the invention, the first layer consists of Ga _1-x Al _x As of the p-type, while the second layer consists of Ga _1-y Al _y As of the n-type. The crystal mixing ratio y is larger than the crystal mixing ratio x, while on the other hand the substrate is a GaAs layer of the p-type.

The drawing shows next to the state of the art exemplary embodiments of the invention. Shown are:

Fig. 1 is a schematic view of a known electrostatic recording apparatus,

Fig. 2 is a schematic view of a Be clearing means in the electrostatic recording apparatus according to Fig. 1,

Fig order. 3 is a plan view of a conventional solid-state light-Diodenan that can be used, for example, within the exposure device according to Fig. 2,

Fig. 4 regulatory a cross section along the line IV-IV through the embodiment illustrated in Fig. 3 solid-state light-Diodenan,

Fig. 5 arrangement, a cross-section along the line VV through the embodiment illustrated in Fig. 3 light-emitting solid state diodes,

Fig. 6 is a view showing the brightness of a conventional light emitting solid state diode array as a function of the location,

Fig. 7 is a plan view of a light emitting solid state diode array according to a first embodiment of the invention,

Fig. 8 shows a cross section through the embodiment illustrated in Fig. 7 diode assembly taken along line VIII-VIII,

Fig. 9 is a partial perspective view shown for explaining the structure of channels that have been established technology using the MESA etching,

Fig. 10a and 10b corresponding cross-sections through the in Fig. Channels illustrated 9, wherein according to Fig. 10a, the angle between a channel wall and the upper level surface and the channel bottom is an obtuse angle, while according to the Fig. 10b, the angle between a Channel wall and the upper level surface or the channel floor is an acute angle,

Fig. 11 is a plan view of a light emitting solid state diode array according to a second embodiment of the invention,

Fig. 12 shows a cross section through the Diodenan arrangement of FIG. 11 along the line XII-XII, and

Fig. 13 is a plan view of a light emitting solid state diode array according to a third embodiment of the invention.

In Figs. 7 and 8, the structure of a light emitting solid state diode array is shown in greater detail according to a first embodiment of the invention. This light-emitting solid-state diode arrangement has a substrate 20 vcm p-type made of GaAs, an epitaxially grown layer 21 of p-type made of Ga _1-x Al _x As, where x indicates the crystal mixing ratio which, depending on the predetermined wavelength of the emitted light, between 0.10 and 0.35, an n-type layer 22 made of Ga _1-y Al _y As grown epitaxially on the p-type layer 21 made of Ga _1-x Al _x As, where y is the crystal mixing ratio represents, individual electrodes 23 made of metallic layers, which have been applied by precipitation in a vacuum, for example by vapor deposition on the layer 22 of the n-type made of Ga _1-y Al _y As, and each have an electrode region 24 with an electrical contact point 24 A, to which a negative potential can be applied, a phosphosilicate glass film 25 (PSG) between the respective electrodes 23 and the n-type layer 22 made of Ga _1-y Al _y As, except in the area of the respective electrical one Contact areas 24 A, and a common electrode 26 made of a metal layer, which is formed for example by precipitation in a vacuum and is located on the entire rear surface of the p-type substrate 20 made of GaAs, to which a positive potential can be applied.

In this solid-state light-emitting diode arrangement, the crystal mixing ratio y is larger than the crystal mixing ratio x, so as to increase the light transmission effect taking into account the wavelength of the light emitted from the p-type layer 21 of Ga _1-x Al _x As and the injection efficiency of the electrons from layer 22 of n-type Ga _1-y Al _y As, and to limit the injected minority carriers from layer 21 of p-type Ga _1-x Al _x As. The respective light-emitting diode regions P are also isolated from one another by channels 27 a and 27 b, which have been produced using the MESA etching technique. The channels 27 a have channel walls that run at an obtuse angle to the respective upper level or channel floor, while the channels 27 b have channel walls that run at an acute angle to the respective upper level or channel floor. The upper level or the channel floor run parallel to the substrate surface. As can be seen from FIGS. 7 and 8, the forward MESA etching channels 27 a run along the row of light-emitting diode regions P or in the row direction, while the reverse MESA etching channels 27 b run between the respective light-emitting diode regions P lie. The individual electrodes 23 extend up to the respective electrode areas 24 and thereby cross the forward MESA etching channels 27 a, whereby they follow the channel structure or concave surface of the channel.

The structure of the channels mentioned and their generation with the aid of the MESA etching technique is described in more detail below with reference to FIG . A semiconductor crystal made of a III-V compound, for example of the zinc blende type, has anisotropy with regard to the chemical etching rate and with regard to the cleavage. A single crystal is used as a semiconductor wafer or wafer with a (100) area for the production of a semiconductor element or chip. According to FIG. 9, a crystal substrate 30 is processed using the MESA etching technique on the (100) surface in the directions <011 <and <01 <perpendicular to it. The MESA etching angle Θa is an obtuse angle for the MESA etching channel M _A , while the MESA etching angle Θb is an acute angle for the MESA etching channel M _B. The MESA etch channel M _A is hereinafter referred to as the forward MESA etch channel, while the MESA etch channel M _{B is} hereinafter referred to as the reverse MESA etch channel. Both channels mentioned correspond to channels 27 a and 27 b.

In FIG. 10a, the course of an electrically conductive layer 23 a made of metal, for example, impact by low or vapor deposition can be generated in vacuo shown a forward mesa etching channel in the area, wherein the layer 23 a on an insulating layer 25 , which in turn is arranged on a substrate 30 . The Fig. 10a shows a section perpendicular to the direction of channel length. A corresponding section through a reverse MESA etching channel is shown in FIG. 10b. Here there is an electrically conductive layer 23 b on an insulation layer 25 , which in turn is arranged in the surface area of the substrate 30 . In the first case according to FIG. 10a, a channel wall lies at an obtuse angle to the channel floor or to the upper level surface, which runs parallel to the substrate surface, while in the latter case according to FIG. 10b, a channel wall lies at an acute angle to the channel floor or to the surface of the substrate 30 runs.

As can be seen 10a and 10b with reference to the Fig., The electrically conductive layer 23 is a non-interrupted in the channel region, while the electrically conductive layer comprises 23 b interruption points in the region of the acute angle etching.

To explain the operation of the light-emitting solid-state diode arrangement according to the first embodiment of the invention, reference is made again to FIGS . 7 and 8.

In operation of the fat body diode array light emitting device, a predetermined voltage is applied between the common positive electrode 26 and the individual negative electrodes 23 to generate a forward electric current flow. In this case, electrons are injected from the layer 22 of the n-type made of Ga _1-y Al _y As into the layer 21 of the p-type made of Ga _1-x Al _x As, so that a light-emitting recombination process takes place and light is emitted from the light emission region P. becomes.

In the described embodiment, each individual electrode 23 is L-shaped, so that a large area is obtained with which a wire 3 can be easily connected. Each individual electrode 23 is also designed such that it is relatively narrow in the electrode region 24 , so that a large and U-shaped light-emitting area is obtained in the light-emitting diode region P.

In particular, the p-type layer 21 can be, for example, a Ga _0.9 Al _0.1 As layer, a charge carrier density of 5 × 10¹⁶ cm ^-3 and a thickness of 20 μm, while the layer 22 of the n-type can be a Ga _0.7 Al _0.3 As layer with a charge carrier density of 2 × 10¹⁷ cm ^-3 and a thickness of 3 µm. First, the layer 21 and then the layer 22 is formed on the (100) surface of the p-type GaAs substrate 20 , which is doped with Zn and has a charge carrier density of 2 × 10¹⁸ cm ^-3 and a thickness of 350 μm. The layers 21 and 22 can be produced, for example, by a liquid phase epitaxy process.

The substrate thus formed is then on its surface treated using the MESA etching technique in such a way that two Forward MESA etch channels in direction <01 <with respect to (100) area can be obtained. Be at the same time multiple reverse MESA etch channels in direction <011 <perpendicular to direction <01 <between the two forward MESA etch channels  educated. This will make a row or row of light-emitting diode areas in the direction of <01 < receive. According to one embodiment, everyone owns Forward MESA etch channel and each reverse MESA etch channel a depth of 5 µm, with light-emitting diode areas with a dimension of 45 µm × 70 µm can be obtained.

Following the etching process, the entire surface thus produced from that already mentioned PSG layer covered, which has a thickness of 0.2 microns, and that grows on the surface. After that, the PSG layer partially removed with the help of fluorine, in a 5 µm × 10 µm area that corresponds to the electrical contact area corresponds.

A metallic layer made of an AuGe alloy / Ni / Au is then evaporated onto the PSG layer on both sides of the light-emitting diode region, to be precise with a thickness of 0.1 μm / 0.2 μm / 0.5 μm, in each case around lines to obtain, each running from an electrode area to a single electrode and crossing the forward MESA etch channel. The PSG layer is layer 25 in FIG. 8, while the metallic vapor deposition layer on layer Au-Ge alloy / Ni / Au is layer 23 .

An electrode 26 made of an Au-Zn alloy / Ni / Au, each with a thickness of 0.1 μm / 0.2 μm / 0.5 μm, is then formed on the entire lower surface of the substrate 20 by vacuum evaporation of metal. There are thus light-emitting areas obtained, each of which is U-shaped, as a result of the covering of the light-emitting diode regions by electrode parts of 10 μm × 30 μm, so that there are three times larger light-emitting regions compared to the prior art.

The described light-emitting solid-state diode arrangement has a total of 16 light-emitting diode areas per mm. Accordingly, 128 light emitting diodes can be used areas in a block or chip of the size 1.6 × 8 mm² accommodate. That means that as exposure device in an electrostatic recorder light emitting diode arrangement with 16 picture elements per mm can be used. With a light emitting Solid state diode arrangement of the MESA type lies the thresholds voltage at 1.5 volts while the electric current at a forward or forward voltage of 2.0 volts larger than 10 mA. The diode arrangement also lasts a reverse voltage or reverse voltage of up to 7 volts out; it emits light with a wavelength of 800 nm.

Compared to the known diode arrangement in the Diode arrangement according to the present application light-emitting area larger while the Efficiency in light generation is higher. Further the light-emitting diode region is more uniform Properties.

As already described, is used as the substrate crystal P-type GaAs crystal used. Of course, an n-type GaAs crystal can also be used be used. In this case the joint receives So electrode on  negative potential while attached to the individual electrodes a positive potential is created.

In addition, the mixed crystal layers on the GaAs substrate also from mixed crystal layers other than GaAlAs layers exist.

In Figs. 11 and 12 is a second execution example of a light emitting solid-Diodenan order described by the invention. The same elements as in FIGS. 7 and 8 are provided with the same reference numerals. The difference from the exemplary embodiment according to FIGS. 7 and 8 is that the electrode regions 24 of the individual electrodes 23 are designed differently. More specifically, each individual electrode 23 has an electrode region 24 which extends from a point 24 B (before the forward MESA etching channel 27 a is reached) to a point 24 c which extends in the direction of extension of the electrode region 24 behind the light-emitting diode region P. lies. In the present case, too, there is an electrical contact point 24 A of the electrode region 24 in the center of the light-emitting diode region P.

According to this second embodiment of the electrode portion 24 is formed symmetrically with respect to the lines L1 and L2, as shown in FIG. 11, which run perpendicular to each other and through the electrical contact point 24 A. The line l2 lies parallel to the line direction. In this case, symmetrical light generation takes place, so that a uniform exposure in the scanning directions or subsequent scanning directions of the electrostatic recording device is obtained.

A third embodiment of the light-emitting solid-diode arrangement according to the invention is shown in Fig. 13. Several pairs of light-emitting diode regions P are present here, while the individual electrodes 23 are arranged and formed symmetrically to a line l3. The width W of the individual electrodes 23 is equal to the sum W₁ + W₂ + W₁ where W₁ is the width of a light-emitting diode area P and W₂ is the gap between two light-emitting diode areas P of said pair. This width W₂ corresponds to the width of a backward MESA etch channel, which, like the forward MESA etch channels, is not included in FIG. 13 for the sake of clarity. Line l3 corresponds to line l2 in FIG. 11, while the widths mentioned are measured parallel to line l3.

Claims (4)

1. Light-emitting linear solid-state diode arrangement consisting of

• a) with a semiconductor device
• a1) a row in the longitudinal direction of the diode arrangement next to each other arranged light-emitting regions (P), each with a pn junction;
• a2) an etching channel ( 27 a), the width of which decreases with increasing depth, and which delimits the light-emitting regions in the longitudinal direction on a respective side;
• a3) in each case one etching channel ( 27 b), the width of which increases with increasing depth, between adjacent light-emitting regions;
• b) an insulating layer ( 25 ) on the front of the semiconductor arrangement, with the exception of a contact opening ( 24 A) over each of the light-emitting region;
• c) a front-side electrode ( 23 ) for each light-emitting region, which extends on the insulating layer from a wire bond region beyond the etching channel, the width of which decreases with increasing depth, over an etching channel region of this etching channel through to a contact region on the associated light-emitting region; and
• d) a back electrode ( 26 ) on the entire back of the semiconductor device; characterized in that
• a1 ′) the light-emitting regions (P) emit the light at right angles to the surface of the Pn junction and thus at right angles to the front of the semiconductor arrangement;
• a2 ′) a second etching channel, the width of which decreases with increasing depth, delimits the light-emitting regions along the other side thereof in the longitudinal direction;
• a3 ′) each etching channel ( 27 b), the width of which increases with increasing depth, runs only between the two etching channels, the width of which decreases with increasing depth;
• b ') the insulating layer transmits the light generated in the light-emitting areas; and
• c ') the front electrodes ( 23 ) are formed as follows;
• - Each front electrode runs in its contact area with the smallest possible width in the longitudinal direction, ie with such a width that just just safe contact to the associated light-emitting area can be made through the contact hole in the insulating layer;
• - The front electrodes alternately extend in opposite transverse directions; and
• - Each front-side electrode has a width in the longitudinal direction in the wire bond area that is greater than the width of the associated light-emitting area.

2. Arrangement according to claim 1, characterized in that the contact area of each front side electrode ( 23 ) is narrower than its etching channel area, but the wire bond area is wider than the etching channel area. 3. Arrangement according to claim 1 or 2, characterized in that the semiconductor arrangement has the following semiconductor layers:

• - a semiconductor substrate ( 20 ) made of p-GaAs;
• a first epitaxial layer made of p-Ga _1-x Al _x As directly on the semiconductor substrate; and
• - A second epitaxial layer made of p-Ga _1-y Al _y As on the first epitaxial layer;
• - whereby these two layers form the pn junction and y is greater than x.

4. Arrangement according to one of the preceding claims, characterized in that the insulating layer ( 25 ) consists of phosphorus-silicate glass.