DE3537796C2 - - Google Patents

Info

Publication number
DE3537796C2
DE3537796C2 DE3537796A DE3537796A DE3537796C2 DE 3537796 C2 DE3537796 C2 DE 3537796C2 DE 3537796 A DE3537796 A DE 3537796A DE 3537796 A DE3537796 A DE 3537796A DE 3537796 C2 DE3537796 C2 DE 3537796C2
Authority
DE
Germany
Prior art keywords
layer
laminate
circuit
catalyzed
photoinitiator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3537796A
Other languages
German (de)
English (en)
Other versions
DE3537796A1 (de
Inventor
Roxy Ni East Brunswick N.J. Us Fan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EIDP Inc
Original Assignee
EI Du Pont de Nemours and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EI Du Pont de Nemours and Co filed Critical EI Du Pont de Nemours and Co
Publication of DE3537796A1 publication Critical patent/DE3537796A1/de
Application granted granted Critical
Publication of DE3537796C2 publication Critical patent/DE3537796C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0505—Double exposure of the same photosensitive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0525—Patterning by phototackifying or by photopatterning adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/102—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding of conductive powder, i.e. metallic powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
    • H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Laminated Bodies (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
DE19853537796 1984-10-26 1985-10-24 Verfahren zur herstellung mehrschichtiger gedruckter schaltungen Granted DE3537796A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/665,002 US4567062A (en) 1984-10-26 1984-10-26 Process for photoformed plastic multistrate using two layer film

Publications (2)

Publication Number Publication Date
DE3537796A1 DE3537796A1 (de) 1986-04-30
DE3537796C2 true DE3537796C2 (enExample) 1989-03-30

Family

ID=24668318

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853537796 Granted DE3537796A1 (de) 1984-10-26 1985-10-24 Verfahren zur herstellung mehrschichtiger gedruckter schaltungen

Country Status (3)

Country Link
US (1) US4567062A (enExample)
JP (1) JPS61114851A (enExample)
DE (1) DE3537796A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4902610A (en) * 1985-08-02 1990-02-20 Shipley Company Inc. Method for manufacture of multilayer circuit board
JPS6364394A (ja) * 1986-09-05 1988-03-22 株式会社日立製作所 プリント配線板の製造方法
US4737446A (en) * 1986-12-30 1988-04-12 E. I. Du Pont De Nemours And Company Method for making multilayer circuits using embedded catalyst receptors
US4859571A (en) * 1986-12-30 1989-08-22 E. I. Du Pont De Nemours And Company Embedded catalyst receptors for metallization of dielectrics
US4720322A (en) * 1987-04-13 1988-01-19 Texas Instruments Incorporated Plasma etching of blind vias in printed wiring board dielectric
US5368884A (en) * 1991-11-06 1994-11-29 Nippon Paint Co., Ltd. Method of forming solder mask
TW277204B (enExample) * 1994-12-02 1996-06-01 Nippon Paint Co Ltd
US5545510A (en) * 1995-03-28 1996-08-13 Mac Dermid, Inc. Photodefinable dielectric composition useful in the manufacture of printed circuits
JP3398557B2 (ja) * 1997-01-29 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 表層配線プリント基板の製造方法
US6016005A (en) 1998-02-09 2000-01-18 Cellarosi; Mario J. Multilayer, high density micro circuit module and method of manufacturing same
US7052824B2 (en) * 2000-06-30 2006-05-30 E. I. Du Pont De Nemours And Company Process for thick film circuit patterning

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157407A (en) * 1978-02-13 1979-06-05 E. I. Du Pont De Nemours And Company Toning and solvent washout process for making conductive interconnections
EP0003801B1 (en) * 1978-02-17 1982-06-09 E.I. Du Pont De Nemours And Company Use of photosensitive stratum to create through-hole connections in circuit boards
US4329620A (en) * 1979-02-23 1982-05-11 Raytheon Company Cathode ray tube with light transparent panel and adhesive therefor
US4454168A (en) * 1982-09-29 1984-06-12 E. I. Du Pont De Nemours And Company Printed circuits prepared from metallized photoadhesive layers
US4469777A (en) * 1983-12-01 1984-09-04 E. I. Du Pont De Nemours And Company Single exposure process for preparing printed circuits

Also Published As

Publication number Publication date
US4567062A (en) 1986-01-28
JPH0217355B2 (enExample) 1990-04-20
DE3537796A1 (de) 1986-04-30
JPS61114851A (ja) 1986-06-02

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee