DE3515013C2 - - Google Patents

Description

The invention relates to a solid-state image sensor in which sta table induction transistors (hereinafter referred to as SIT) as Image elements are used.

For conventional solid-state image sensors for use in Video cameras, facsimile machines, etc. have been charge transfers facilities such as BBD (Bucket Brigade Device; bucket chains circuit), CCD (Charge Coupled Device) or MOS transistors suggested. These solid-state image sensors have ver various disadvantages, such as the leakage of La charge transfer and low light sensitivity.

To avoid these disadvantages, so-called SIT have recently been used for solid-state image sensors have been proposed. The SIT is a kind of phototransistor, which is both a photoelectric order conversion as well as a photoelectric charge storage possible. It has several advantages, such as a high input impedance, high response speed, lack of saturation, ge low noise and low power consumption etc. in Comparison to field effect transistors or junction transistors to disturb. A solid state built using SIT Image sensor therefore has a high sensitivity, a high on speech speed and a wide dynamic range.  

Such a solid-state image sensor is in Japanese Patent application 105, 672/83 described.

Fig. 1 shows a section through a picture element of a known solid-state image sensor (US-PS 44 27 990). The SIT 1 has a so-called "vertical arrangement", in which the drain region is formed by an n + substrate 2 and a source region by an n + region 4 in an n ^- epitaxial layer 3 , which has grown on the n⁺ substrate 2 and forms the channel region. In the epitaxial layer 3 , a p⁺ gate region 5 is also provided for signal storage, which surrounds the n⁺ source region 4 , while the electrode 7 is attached to the gate region 5 via an insulating film 6 . In this way, a gate electrode with a so-called MIS structure is formed, ie an arrangement of metal electrode / isolate the film / semiconductor gate region. The impurity concentration in the n ^- epitaxial layer 3 , which forms the channel region, is set so low that the channel region is depleted even when the bias voltage applied to the gate electrode 7 is zero volts, so that a pinch-off voltage is present a high potential barrier is obtained.

The operation of SIT 1 is explained below. If light falls on the channel region 3 and the gate region 5 without a bias voltage being applied between the drain and source, holes are induced by electron-hole pairs and stored in the gate region 5 , while electrons from the drain region 2 to Ground connection are dissipated. The holes stored in the gate region 5 in accordance with the incident light increase the potential of the gate region 5 and lower the potential barrier of the channel region 3 in accordance with the intensity of the incident light. If a bias voltage is placed between the drain and source and also a forward bias to the gate electrode 7 , a current flows between the drain and source in accordance with the amount of holes stored in the gate region, so that an output signal can be obtained that is amplified according to the intensity of the incident light. The light amplification factor S results from the equation

where 2 a the inner diameter of the annular gate region 5 , l ₁ the depth of the gate region 5 and l ₂ are the distance between the gate and drain regions. In the SIT 1 shown, the light amplification factor S is normally 10 3 and is therefore an order of magnitude better than with bipolar transistors. As can be seen from the above equation, it is necessary to achieve large amplification factors, the distance 2 a small, the To make the depth of the epitaxial layer 3 and the gate region 5 large. For example, to obtain a gain factor S of 10³ to 10⁴, the following values must be adhered to: l ₁ = 2 to 3 µm and l ₂ = 5 to 6 µm.

In the solid-state image sensor described above, it is necessary to arrange an isolation region 8 between adjacent SITs, so that the signal charges induced in the individual SIT are isolated. This insulation is achieved by ordinary insulation processes, such as application of an oxide film, diffusion or V-shaped recesses. In the example shown, the insulation region 8 extends from the surface of the epitaxial layer 3 to the substrate 2 , so that difficulties arise in the formation of the insulation region 8 in the case of a strong epitaxial layer 3 . Since it is also necessary to make the gate region 5 strong in order to achieve large amplification factors S , diffusion methods are ruled out. If the gate region 5 is also formed relatively strongly, an undesirable spectral sensitivity arises due to light absorption in the gate region 5 . For this reason, the sensitivity of the known SIT is restricted by the given structure.

If a so-called "self-adjustment" is to be carried out during the integration of the source-gate arrangement, it is necessary to cover the source region 4 with a mask when forming the gate region 5 . This process is complex and expensive in the prior art. On the other hand, if the source-gate arrangement is integrated, the breakdown voltage between source and drain is relatively low, so that leakage currents can occur.

The invention has as its object the above parts to overcome and to create a solid-state image sensor fen, which can be easily integrated, a high sensitivity has ability and is inexpensive to manufacture.

A solid-state image sensor that solves this problem is with its Refinements characterized in the claims.

Since, according to the invention, the SIT of the individual picture elements is a MOS Have gate construction without any gate diffusion layer is provided, a so-called "self-adjustment rungsverfahren "for integrating the source-drain arrangement with with fewer masks. Because this procedure advantageous in the formation of peripheral circuit arrangements is used, a solid-state image sensor with high Manufacturing integration density inexpensively. Since the gate elec trode can be made relatively thin, the solid state Image sensor has a high sensitivity in the entire range of long to short wavelengths. Also with which he inventive solid-state image sensor the reset of the ge stored light charge carriers more easily and securely than with Carry out image sensors with a gate diffusion layer. Can too the breakdown voltage between gate and source is relatively large be made. Even the fluctuations in the characteristic Data of the individual picture elements can be kept relatively low will.  

Embodiments of a solid-state image according to the invention sensors are explained in more detail using a drawing. It shows or show

Fig. 2A-2C are schematic illustrations of a first execution example of a pixel of a solid-state SIT image sensor;

. Figs. 3A-3D and 4A-4D, schematic illustrations of the loading drive of the SIT-Bildelemen shown in Figures 2A-2C tes.

Fig. 5A and 5B are schematic representations of the circuit of the solid-state image sensor;

FIG. 6A-6F signals pulse shapes of the vertical and horizontal scanning;

FIGS. 7A-7H are schematic illustrations of the process provide for the Her in Fig solid-state image sensor shown. 5A;

FIG. 8A-8C are schematic representations of a second example of an exporting approximately SIT image element for a solid-state image sensor;

. Figs. 9A-9D and 10A-10D are schematic representations of the loading drive of the SIT shown in Figures 8A-8C. and

FIG. 11A-11J are schematic views of the method for herstel len of the solid-Bildsen sors shown in FIGS. 8A-8C.

Figs. 2A and 2B are a plan view and a cross-sectional forms of a solid-state image sensor of a first embodiment of a SIT, which is a pixel. In this exemplary embodiment, the SIT 11 has an n ^- semiconductor substrate 12 , a circular n + source diffusion layer 13 which is formed in the surface of the substrate 12 , a source electrode 14 which is arranged in the source diffusion layer 13 is, a MOS gate arrangement, which consists of a gate insulating film 15 , which is arranged on the surface of the substrate 12 and surrounds the source diffusion layer 13 , and an annular gate electrode 16 , which on the Gate insulating film 15 is arranged and made of polysilicon, SnO₂, ITO or the like. An n⁺-drain diffusion layer 17 is attached to the back of the substrate 12 . The gate electrode 16 is covered by an insulating layer 18 . The gate insulating layer 15 is evenly distributed on the surface of the substrate 12 except in the portion corresponding to the source diffusion layer 13 of the SIT 11 . Furthermore, an n⁺ diffusion layer 19 is arranged between adjacent SIT 11 , so that the individual SIT 11 are electrically and optically isolated.

In a SIT 11 with the MOS structure shown in FIGS . 2A and 2B (hereinafter referred to as MOSSIT), the concentration of the substrate 12 (n ^- ) is preferably less than 10 13 cm ^-3 , while the depths x _{j of} the source diffusion layer 13 and the diffusion layer 19 for insulation assume approximately the same values, preferably less than 0.2 μm. The diameter Φ ₁ of the source diffusion layer 13 is less than 1.0 microns, while the outer diameter Φ ₂ of the gate electrode 16 has a thickness of 2.0 to 6.0 microns and the thickness of the gate insulating layer 15 values between 200 and 1000 Å (0.02 to 0.1 µm).

Fig. 2C shows an equivalent circuit diagram of the MOSSIT 11, wherein a gate voltage V _G on the gate terminal 21 to the gate electrode of de 16, a source voltage V _S via the source terminal 22 to the source electrode 14, a drain voltage V _D to the drain terminal 23 , which is further connected to the drain diffusion layer 17 , and an insulation voltage V _ISO to the insulation terminal 24 , which is further connected to the diffusion layer 19 for insulation, are applied.

The operation of the MOSSIT 11 will be explained with reference to FIGS . 3A-3D and 4A-4D. FIGS. 3A-3D illustrate pulse shapes of the insulation voltage V _ISO, the gate voltage V _G, the drain voltage-V _D and source voltage V _S, where on the horizontal axis represents time and the vertical axis is the voltage give is. The light reception period of the MOSSIT 11 is composed of the storage period T ₁, the readout period T ₂ and the reset period T ₃, during which the insulation voltage V _ISO and the drain voltage V _{D are} at the constant value V _{D 2} (<0) are kept. During the storage period T ₁, the gate voltage V _{G is kept} at a storage gate potential V _{G 1} (<0) and the source voltage V _S at a value V _{S 2} (= V _{D 2} ), which corresponds to the drain voltage V _D. During the readout period T ₂ is held the gate voltage V _G on the gate read voltage V _{G 2} (V _{G 1} <V _G2 <0), while the source voltage V _S at the ground potential V _{S 1} (< V _{S 2} ) is held. During the reset period T ₃, the gate voltage V _{G is held} at the reset gate voltage V _{G 3} (<0) and the source voltage V _S assumes the ground potential V _{S 1} .

Referring to FIG. 4A, the depletion layer extends immediately after a reset 31 of the interface between the gate insulating layer 15 strat the and the substrate 12 in the sub inside. This expansion of the depletion layer 31 is maintained until the readout period T 2 begins when no light falls on the gate electrode 16 . However, if light falls on the gate electrode 16 , electron-hole pairs are generated in the depletion layer 31 . The holes thus formed are stored in the surface of the substrate 12 immediately below half of the gate insulating layer 15 as shown in FIG. 4B, so that the expansion of the depletion layer is reduced and the potential barrier with respect to the electron movement in the vertical direction is compared to Fig. 4A reduced (vertical: perpendicular to the main plane).

If the gate voltage V _{G is increased} from V _{G 1} to V _{G 2} after the storage period T 1 has elapsed, the potential barrier for the electrons further decreases, in accordance with the increase in the gate voltage V _G according to FIG. 4C, so that a ver amplified signal current flows between the source and drain. In this case it was found experimentally that the output current is approximately proportional to the integrated amount of light during the storage period T ₁.

If the gate voltage V _{G is increased} from the value V _{G 2} to V _{G 3} (< V _{S 1} ) after the readout period T ₂ has elapsed, then those in the surface of the substrate 12 immediately below the layer 15 insulating the gate stored holes 32 via the source diffusion layer 13 and the source electrode 14 ge as shown in FIG. 4D. If the gate voltage V _G and the source voltage V _S thereafter assume the values V _{G 1} and V _{S 2} after the reset period T ₃ has elapsed, the next light reception cycle is started. It should be noted that the movement of the holes 32 stored directly beneath the gate insulating layer 15 in adjacent picture elements is prevented because an insulation voltage is applied to the diffusion layer 19 , thereby creating a high barrier to hole movement in horizontal Direction is generated.

FIG. 5A shows the circuit diagram of a solid-state image sensor in which the MOSSIT shown in FIGS . 2A-2C are used. FIG. 5B is a top view of a portion of the solid-state image sensor shown in FIG. 5A. There are m × n MOSSIT 11-11 to 11- mn arranged in a matrix and image signals are read out from the individual image elements one after the other by means of an XY addressing, ie a source-gate selection method. The gate connections of the individual MOSSIT of lines 11-11 to 11- m 1,. . ., 11-1 n to 11- mn , which in the X direction with the associated row lines 41-1 ,. . ., 41- m are connected with vertical scanning signals Φ _{G 1} ,. . ., Φ _Gm fed, which leads from the vertical scanning circuit 42 into the individual lines 41-1 ,. . ., 41- m can be entered. To the source connections of the individual MOSSIT in columns 11-11 to 11- m 1. . ., 11-1 n to 11 - mn , which are arranged in the Y direction and with the associated column lines 43-1,. . ., 43 - n are connected, the individual column lines 43-1,. . ., 43- n is connected, which in turn with the ground line 47 and via column selection transistors 44-1,. . ., 44- n and inverting selection transistors 45-1,. . ., 45- n are connected to the video line 46 . Horizontal scanning signals Φ _{S 1} ,. . ., Φ _Sn are connected to the gate connections of the column selection transistors 44-1,. . ., 44- n from the horizontal scanning circuit 48 and inversion signals of these horizontal scanning signals are also applied to the gate terminals of the reverse selection transistors 45-1,. . ., 45- n created. Furthermore, the drain connections of all MOSSIT 11-11 to 11- mn of the picture elements are connected together to the video line 46 and a video voltage V _DD is applied to the drain connections via a load resistor 49 . The same voltage (V _DD ) is also applied to the diffusion layers of the insulation between adjacent picture elements.

FIGS. 6A-6C show the pulse of the vertical scanning signals Φ _{G 1, G 2} Φ. . ., which in the row lines 41-1, 41-2,. . . can be entered. FIGS. 6D-6F show the pulse of the hori zontal scanning signals Φ _{S 1, S 2} Φ. . ., Which is connected to the gate connections of the column selection transistors 44-1, 44-2,. . . be created. The vertical scanning signals Φ _{G 1} , Φ _{G 2} . . ., Which are represented by the readout gate voltage V _{Φ G} with a small amplitude and the reset voltage V _{Φ R} with a large amplitude, are set to the value V _{Φ G} during a line scanning period t _H and during a blanking period to the beginning of the next horizontal scanning line of the fol lowing to the value _{Φ R} V set. The horizontal scanning signals Φ _{S 1} , Φ _{S 2} ,. . . are used to select the column lines and are set to such voltage values that the column selection transistors 44-1 , 44-2,. . . turned off and the reverse selection transistors 45-1 , 45-2,. . . Become conductive, while a signal at higher amplitude, the column selection transistors 44-1 , 44-2 ,. . . conductive and the reverse selection transistors 45-1 , 45-2,. . . does not conduct.

The operation of the solid-state image sensor shown in FIGS . 5A and 5B will be explained below with reference to the pulse shapes shown in FIGS . 6A-6F. If the signal Φ _{G 1} assumes the read-out level V _{Φ G} according to a command from the vertical scanning circuit 42 , a first MOSSIT row is selected from the MOSSIT 11-11 to 11-1 n , which is connected to the row line 41- 1 are connected and the column selection transistors 44-1 to 44- n are switched in succession by means of the signals Φ _{S 1} to Φ _Sn , which are supplied by the horizontal scanning circuit 48 , so that on the video line 46 the image signals are consecutive MOSSIT 11-11 , 11-12 ,. . ., 11-1 n can be read out. Then the MOSSIT series from the MOSSIT 11-11 to 11-1 n is reset by means of the signals Φ _{S 1} to Φ _Sn high level, which are generated simultaneously when the signal Φ _{G 1} assumes the high level V _{Φ R.} If the signal Φ _{G 2} assumes the read-out level V _{Φ G} , a second MOSSIT row is selected from the MOSSIT 11-21 to 11-2 n , which are connected to the row line 41-2. Then the image signals of the MOSSIT 11-21 , 11-22 ,. . ., 11-2 n are read out one after the other and all MOSSIT 11-21 to 11-2 n are reset at the same time. Thereafter, subsequent image signals are read out in the same manner as described above to obtain the video signals for a field scan.

In the solid-state image sensor described above, the source and drain of an unselected SIT are mutually connected by means of the reverse selection transistors 45-1 to 45- n so that no signal is generated by the unselected MOSSIT.

In the solid-state image sensor shown in Fig. 5A, the MOSSIT 11-11 to 11- mn and peripheral circuits such as the vertical scanning circuit 42 , the column selection transistors 44-1 to 44- n , the reverse selection transistors 45-1 to 45- n and the horizontal scanning circuit 48 formed on the same sub strat.

The steps for producing such an image sensor and the peripheral circuits are explained below with reference to FIGS . 7A-7H.

First, according to Fig. An insulating layer 51 having a thickness of about 7000 Å (0.7 microns) uniformly on the upper surface of the substrate formed 7A 12 by means of, for example, thermal oxidation. Then, a resistive layer 53 is formed on the light receiving section 52 by means of photo-lithography, and then an insulating layer in the section in which a sink is provided for the peripheral circuits 54 is etched away, so that impurities in the form in this area of acceptors, such as boron, can be deposited with a concentration of approximately 10 13 cm ^-3 . Then, an n⁺-drain layer 17 for the light receiving element is formed on the back of the substrate 12 and then the resistance layer 53 for the formation of the depression is removed and a depression with a thickness of about 5 μm is formed as shown in FIG. 7B . Then, an insulating layer corresponding to the portion at which the gate insulating layer is to be formed is removed by etching after a resistive layer 56 is formed by photolithography in the portions other than the etched portion, so that a gate insulating Film 15 is formed with a thickness of about 200-1000 A (0.02-0.1 microns) as shown in FIG. 7C.

Then, as shown in FIG. 7D, an electrode layer 57 with a thickness of about 500-3000 Å (0.05-0.3 μm) is formed to form the gate electrode, and a resistance layer 58 which covers the gate electrode of the MOSSIT in the light Receiving area and the NMOSFET in the peripheral circuits is formed by means of photo-lithography on the electrode layer 57 . Thereafter, 7E, the electrode layer will accordingly. To gate electrodes to form selec tively removed by etching of 57 16 MOSSIT and the NMOSFET, after which, using the gate electrodes 16 as a mask, the n⁺-source diffusion layers 13, the n⁺ -Diffusion layers 19 for the isolation of the MOSSIT, the n⁺-source diffusion layers 59 , and the n⁺-drain diffusion layers 60 of the NMOSFET are formed by means of ion injection in such a way that arsenic or phosphorus with a concentration of approximately 10¹⁵- 10¹⁶ cm ^{-3 is} deposited in the substrate 12 .

Then, the resistive layer 58 used in the formation of the gate electrode is removed and the insulating layer 18 is formed on the surface of the gate electrode 16 . Then 7F is corresponding to FIG. 61, a resistor layer formed by photo-lithography and in the resistive layer 61 contact holes 62 are provided to the source electrodes, the electrodes to isolate the light-receiving elements, as well as the source and drain Form electrodes of the NMOSFET, which represent the peripheral circuits. Then, the resistance layer 61 , which was used in the formation of the contact holes, is removed and the source electrodes, the electrodes for the isolation of the light receiving elements and the source and drain electrodes of the NMOSFET of the peripheral circuits are formed. Then, as shown in FIG. 7G, the resistance layer 63 is formed by means of photo-lithography and a residual electrode layer is removed by means of etching, so that the source electrodes 14 and the insulation electrodes (not shown) of the light-receiving elements and the source electrodes 64 and the drain electrodes 65 of the NMOSFET of the peripheral circuits are formed. Thereafter, the resistive layer 63 on these electrodes is removed as shown in FIG. 7H, so that the light receiving elements with their MOSSIT and the peripheral circuits with their NMOSFET are formed on the same substrate 12 .

In this way, both the light receiving elements as well as the peripheral circuits on the same substrate train, with only a small number of masks, about 5 or 6, are required, so that the production is relatively simple and is inexpensive. Because there is a so-called self-adjustment can be carried out, the products are relatively small and still precisely shaped.

FIGS. 8A and 8B show a plan view and a sectional view of a second embodiment of a solid-Bildsen sors with MOSSIT which respectively form a pixel. A MOSSIT 71 has a double layer structure such that a taxi Epi e-coating 73 of n ^- -Eigen semiconductor material on the upper surface of the substrate is formed 72nd Also provided are: a circular n kreis-source diffusion layer 74 , which is formed in the surface of the epitaxial layer 73 , a source electrode 75 , which is arranged on the source diffusion layer 74 , a MOS gate arrangement with a Gate insulating layer 76 , which is arranged on the epitaxial layer 73 which surrounds the source diffusion layer 74 , a ring-shaped gate electrode 77 made of polysilicon, SnO₂, ITO or the like, and an n⁺ diffusion layer 78 , which both serves as a drain as well as an isolation area. Furthermore, the surface of the gate electrode 77 is covered by an insulating layer 79 . The gate insulating layer 76 is uniformly distributed on the surface of the epitaxial layer 73 with the exception of the portion which corresponds to the source diffusion layer 74 of the MOSSIT 71 concerned.

In the MOSSIT 71 shown in FIGS . 8A and 8B, when using an n ^- epitaxial layer 73, a concentration and thickness of the epitaxial layer 73 of 10 13 cm ^-3 or 8 μm are provided, while the depths x _{j of} the source diffusion layer 74 and the drain and insulation layer 78 assume approximately the same values, namely below 0.2 μm. The diameter Φ ₁ of the source diffusion layer 74 is preferably less than 1.0 microns, the diameter Φ ₂ of the gate electrode 77 is in the range between 2.0-6.0 microns and the thickness of the gate insulating layer 76 is Range of 200-1000 Å (0.02-0.1 µm).

Fig. 8C shows an equivalent circuit diagram for the MOSSIT 71st The gate voltage V _{G is applied} to the gate electrode de 77 via the gate connection 81 and the source voltage V _{S is applied} to the source electrode 75 via the source connection 82 . Furthermore, the drain voltage V _{D is} input via the drain connection 83 , which in turn is connected to the drain and the insulating diffusion layer 78 , while a substrate voltage V _{SUB is applied} via the substrate connection 84 to the substrate 72 .

The operation of the MOSSIT 71 is explained below with reference to FIGS . 9A to 9D and 10A to 10D. FIGS. 9A-9D show pulse shape of the substrate voltage V _SUB, the gate voltage V _G, the drain voltage V _D and source voltage V _S, plotted on the horizontal axis represents time and the vertical axis represents voltage are. A light reception period T of the MOSSIT 71 is composed of the memory period T ₁, the read-out period T ₂ and the reset period T ₃ together. During the light reception period T , a constant voltage V _{D 2} (<0) is applied to the drain terminal 83 as the drain voltage V _D and a reverse voltage V _{SUB 1} (lower than the ground potential) is the substrate voltage V _{SUB applied} to the substrate terminal 84 . During the storage period T ₁, the gate voltage V _{G is set} to a memory gate voltage V _{G 1} (<0) and the source voltage V _S to the value V _{S 2} (= V _{D 2} ), which corresponds to the drain voltage V _D. During the readout period T ₂, the gate voltage V _G assumes the value V _{G 2} (V _{G 1} < V _{G 2} <0) and the source voltage V _S is reduced to the ground potential V _{S 1} (< V _{S 2} ) set. During the reset period T ₃ only the gate voltage V _{G is set} to the reset value V _{G 3} (<0), while the source voltage V _{S is kept} at the value of the ground potential V _{S 1} .

Immediately after performing the reset, as shown in FIG. 10A, the depletion layer 91 will largely extend into the substrate from the interface between the gate insulating layer 76 and the epitaxial layer 73 . This state is maintained until the read-out period T 2 begins if no light falls on the gate electrode 77 . However, if light falls on the gate electrode 77 , electron-hole pairs are generated in the depletion layer and its neighboring regions and the holes 92 formed in this way are in the surface of the epitaxial layer 73 immediately below the gate insulating layer 76 according to FIG . 10B stored, so that the expansion of the depletion layer 91 is reduced and, accordingly, the potential barrier for the moving in the direction Vertika ler electrodes shown in FIG. 10A is lowered.

If the gate voltage V _{G is increased} from the value V _{G 1} to the value V _{G 2} after the storage period T _{1 has} elapsed, as shown in FIG. 10C, the potential barrier for the electrons by the gate voltage V _G rises significantly decreased so that an amplified signal current flows between the source and drain. It has been found experimentally that this signal current is approximately proportional to the amount of light falling during the storage period T 1.

If the gate voltage V _{G is} further increased from the value V _{G 2} to the value V _{G 3} (< V _{S 1} ) after the elapse of the readout period T ₂, then those in the surface of the epitaxial layer 73 immediately below that which isolates the gate Layer 76 stored holes 92 leads partially via the source diffusion layer 74 and the source electrode 75 and partially via the substrate 72 . Thereafter, the gate voltage V _{G is set} to the value V _{G 1} ge and the source voltage V _S assumes the value V _{S 2} after Ver the reset time period T ₃ so that the next light reception period can begin. It should be noted that the movement of the holes 92 stored directly beneath the layer 76 which isolates the gate into adjacent picture elements is prevented by the fact that a high potential barrier with respect to the holes moving in the transverse direction (parallel to the main plane) exists, which is caused by the Drain and the insulating diffusion layer 78 is formed, to which the drain voltage V _{D is} applied, wherein the substrate 72 has a predetermined potential due to the substrate voltage V _SUB , which can be amplified by a voltage in the reverse direction.

Since in the MOSSIT 71 described above, the holes are produced in deep sections of the epitaxial layer 73 and since the holes produced by light above the saturation limit are dissipated into the substrate 72 , so-called overexposure and smearing cannot occur.

In a further exemplary embodiment of a solid-state image sensor, m × n MOSSIT are arranged in a matrix in accordance with FIGS . 8A-8C and the reading is carried out using a circuit arrangement corresponding to FIG. 5A. Also in this embodiment, the light receiving elements with their MOSSIT and the peripheral circuits are formed on the same substrate.

The successive steps for forming the light receiving elements and the peripheral circuits are explained below with reference to FIGS . 11A-11J.

First, Figure 11A is a resistor layer accordingly. Configured 102 on the surface of a light-receiving section 101 of the p-type substrate 72, and such as arsenic or phosphorus will be deposited in an area peripheral to wel chem a sink circuits is donor impurities, 103 is provided. An n layer 104 is formed for the electrical insulation of the depression from the substrate 72 . In this case, the concentration of the donor impurities is about 10¹⁶ to 10¹⁷ cm ^-3 after the manufacturing process is completed.

Then, the insulating layer on which the donor impurities are deposited, and on the light-receiving section 101 formed resistive film 102 is removed, and an n ^- - or an epitaxial layer 73 having intrinsic conductivity grows in accordance with Fig. 11B.

Then, as shown in FIG. 11C, a field insulation layer 105 having a thickness of about 7000 Å (0.7 μm) is uniformly formed on the surface of the epitaxial layer 73 by means of thermal oxidation. The resistive layer 106 is then formed on the light receiving section 105 by means of photo-lithography and then an insulating layer corresponding to the section in which a depression for the peripheral circuits 104 is to be formed is etched away, so that contaminants, for example boron, are also removed a concentration of about 10 13 cm ^-3 can be deposited in this area. The resistive layer 106 for the formation of the well is then removed and a p-well 107 with a depth of approximately 5 μm is produced as shown in FIG. 11D. Then, the insulating layer on the portion on which the gate insulating layer is to be formed is removed by etching after the resistance layer 108 is formed in the other area by means of photo-lithography, and the gate insulating layer 76 is also formed a thickness of 200-1000 Å (0.02-0.1 µm) as shown in Fig. 11E.

Then, as shown in FIG. 10F, an electrode layer 109 is formed with a thickness of about 500-3000 Å, and a resistance layer 110 for forming the gate electrodes of the MOSSIT of the light receiving elements and the NMOSFET of the peripheral circuits is formed on the electrodes by means of photo-lithography layer 109 molded. Then, corresponding to FIG. 11G 109 removed by etching to form the electrode layer to the individual gate electrodes 77 of the NMOSFET and MOSSIT. Using the gate electrodes 77 as a mask, source diffusion layers 74 and the N + N + drain diffusion layers and insulating layers 78 of the MOSSIT and n⁺- source diffusion layers 111 and n⁺-type drain diffusion layers 112 of the NMOSFET formed such that impurities, such as arsenic or phosphorus, are deposited by ion injection with a concentration of about 10¹⁵-10¹⁶ cm ^-3 .

The resistance layer 110 for forming the gate electrodes is then removed and the insulating layer 79 is deposited on the surface of the gate electrode 77 . Then, the resistive layer is accordingly FIG. 11H 113 formed by means of photo-lithography, and it will contact holes 114 for the generation of the source electrodes and the drain and Isola tion electrodes of the light-receiving elements and the source electrode and the drain Electrodes of the NMOSFET of the peripheral circuits are formed. Then, the resistance film 113 used in the formation of the contact holes is removed, and an electrode layer is formed for the formation of the source electrode and the drain and isolation electrodes as well as the source and drain electrodes of the NMOSFET. Thereafter shows a resistive layer accordingly. 11I formed 115 by means of photo-lithography and residual electrode layers are removed by etching (not shown) to the source electrodes 75 and drain and Iso lationselektroden the light-receiving elements and the source electrodes 116 and the drain electrodes of the NMOSFET to form the peripheral circuits. A resistive layer 115 on these electrodes is then removed to finally form the MOSSIT and also the peripheral circuits with the NMOSFET on the same substrate 72 as shown in FIG. 11J.

In this way, as with the previously described Aus example, both the light receiving element and the peripheral circuits on the same substrate in simpler and manufactured inexpensively, with only a small Number of masks, namely 5 or 6 are required.  

In the MOSSIT 11 shown in FIGS . 2A-2C, n ^- semiconductor material or self-semiconductor material has been used for the substrate, but semiconductors with more complex layer arrangements, such as n ^- / n⁺-, self- Semiconductors ter / n⁺- p ^- / n⁺ arrangements are used. Even in these cases, the manufacturing process is not very complex, since only an epitaxial growth to form the n ^- , Eigenlei line or p ^- semiconductor layer on the n⁺ substrate has to be added to the steps shown in FIGS . 7A-7H , the number of masks to be used also 5 or 6 be. If semiconductors with a more complicated layer structure are used, the parasitic drain resistance can be reduced in comparison with the MOSSIT 11 of FIGS . 2A-2C and the isolation between the picture elements with respect to the holes can be carried out reliably. Since the length of the potential barrier can also be controlled in accordance with the thickness of the epitaxial layer, more possibilities open up in the manufacturing process and in the construction of the structure of the solid-state image sensor. Both in the modified exemplary embodiment described above and in the exemplary embodiments explained with reference to FIGS . 2-7, the insulation can also be produced by an insulating recess instead of the n⁺ diffusion layer. A p-type substrate 72 is used in the MOSSIT 71 shown in FIGS . 8A-8C, but it is also possible to use an insulating substrate instead. In the exemplary embodiments, n-channel arrangements are provided, but p-channels can also be used instead. In this case, the polarities of the applied voltages are reversed. In the case of a solid-state image sensor with source-drain selection according to FIG. 5A, the gate voltage V _{Φ G} during the readout period according to FIGS. 6A-6C can assume the same level as during the storage period. Since light charge carriers can also be stored without the reverse selection transistors 45-1 to 45- n , these reverse selection transistors can also be omitted. Also, the solid-state image sensors according to the invention are not limited to the source-gate selection shown, rather a drain-gate selection or a source-drain selection can also be provided to derive the video signal during the raster scanning.

Claims (17)

1. Solid-state image sensor with a plurality of matrix-shaped, on a semiconductor substrate ( 12; 72 ) arranged, isolated image elements, each having a static induction transistor ( 11; 71 ), characterized in that
that on the surface of the semiconductor substrate, the gate ( 16; 77 ) of the static induction transistor ( 11; 71 ) is formed in an insulated manner by means of an insulating layer ( 15, 76 ) that a diffusion layer ( 19; 78 ) in order to isolate the picture elements from one another Surface of the semiconductor substrate ( 12; 72 ) is formed and
that for generating a potential barrier in the direction perpendicular to the surface of the semiconductor substrate ( 12; 72 ) a processing zone ( 31; 91 ) is provided in the semiconductor substrate. 2. Solid-state image sensor according to claim 1, characterized in that each static induction transistor ( 11 ) has a first main electrode region ( 14 ) of a certain conductivity type, which is formed in the surface of the semiconductor substrate ( 12 ), which is the gate insulating layer ( 15 ) which is formed in the surface of the semiconductor substrate ( 12 ) and encompasses the main electrode region ( 14 ), and the gate electrode ( 16 ) on which the gate insulating layer ( 15 ) is formed. 3. Solid-state image sensor according to claim 2, characterized in that the static induction transistor ( 11 ) has a second main electrode region ( 17 ) which is formed on the other surface of the semiconductor substrate ( 12 ). 4. Solid-state image sensor according to one of the preceding claims, characterized in that the semiconductor substrate ( 12 ) is of the n ^- conductivity type. 5. Solid-state image sensor according to one of claims 1-3, characterized in that the semiconductor substrate ( 12 ) has intrinsic conduction. 6. Solid-state image sensor according to one of claims 2 to 5, characterized in that the insulating diffusion layer ( 19 ) is arranged around the gate insulating layer ( 15 ). 7. Solid-state image sensor according to claim 2, characterized in that the static induction transistor ( 71 ) has a further main electrode region ( 73 ) of a certain conductivity type, which is formed in the semiconductor substrate ( 72 ) and the gate insulating layer ( 76 ) surrounds. 8. Solid-state image sensor according to claim 7, characterized in that the semiconductor substrate ( 72 ) has a first semiconductor layer ( 74 ) and a second semiconductor layer ( 73 ) of a certain conductivity type, which layer on the first semiconductor ( 74 ) is applied. 9. Solid-state image sensor according to claim 8, characterized in that the first and second semiconductor layers ( 74 and 73 ) have n⁺ or n ^- conductivity. 10. Solid-state image sensor according to claim 8, characterized in that the first and second semiconductor layers ( 74 and 73 ) have n⁺ or intrinsic conductivity. 11. Solid-state image sensor according to claim 8, characterized in that the first and second semiconductor layers ( 74 and 73 ) have n⁺ or p ^- conductivity. 12. Solid-state image sensor according to one of claims 2 or 7, characterized in that the gate insulating layer ( 15, 76 ) is formed by an oxide of the material forming the semiconductor substrate. 13. Solid-state image sensor according to one of the preceding claims, characterized in that the gate electrode ( 16, 77 ) is formed from polysilicon, SnO₂ or ITO. 14. Solid-state image sensor according to one of the preceding claims, characterized in that the static induction transistor ( 11, 71 ) has an insulating layer ( 18, 79 ) which covers the gate electrode ( 16, 77 ). 15. Solid-state image sensor according to one of the preceding claims, characterized in that peripheral circuits ( 103 ) including MOSFET are provided, which are formed on the same semiconductor substrate ( 72 ). 16. A method for producing a solid-state image sensor according to one of claims 2 to 15, characterized in that the first electrode region is formed in the surface of the semiconductor substrate ( 12 ) and that the gate insulating layer ( 76 ) as a mask the manufacturing is used. 17. The method according to claim 16, characterized in that gate electrodes ( 77 ) are used as a mask in the manufacture of the insulating diffusion layer ( 78 ).