DE3485258D1 - Alu mit uebertragslaengendetektion. - Google Patents

Alu mit uebertragslaengendetektion.

Info

Publication number
DE3485258D1
DE3485258D1 DE8484401849T DE3485258T DE3485258D1 DE 3485258 D1 DE3485258 D1 DE 3485258D1 DE 8484401849 T DE8484401849 T DE 8484401849T DE 3485258 T DE3485258 T DE 3485258T DE 3485258 D1 DE3485258 D1 DE 3485258D1
Authority
DE
Germany
Prior art keywords
alu
length detection
transmission length
transmission
detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484401849T
Other languages
German (de)
English (en)
Inventor
Daniel Dobberpuhl
Edward J Mclellan
Gilbert Wolrich
Robert Yodlowski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE3485258D1 publication Critical patent/DE3485258D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8484401849T 1983-09-20 1984-09-18 Alu mit uebertragslaengendetektion. Expired - Fee Related DE3485258D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/534,018 US4623981A (en) 1983-09-20 1983-09-20 ALU with carry length detection

Publications (1)

Publication Number Publication Date
DE3485258D1 true DE3485258D1 (de) 1991-12-19

Family

ID=24128369

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401849T Expired - Fee Related DE3485258D1 (de) 1983-09-20 1984-09-18 Alu mit uebertragslaengendetektion.

Country Status (5)

Country Link
US (1) US4623981A (enrdf_load_stackoverflow)
EP (1) EP0136939B1 (enrdf_load_stackoverflow)
JP (1) JPS60144825A (enrdf_load_stackoverflow)
CA (1) CA1216951A (enrdf_load_stackoverflow)
DE (1) DE3485258D1 (enrdf_load_stackoverflow)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143341A (ja) * 1984-08-07 1986-03-01 Nec Corp 加算回路
GB8531380D0 (en) * 1985-12-20 1986-02-05 Texas Instruments Ltd Multi-stage parallel binary adder
US4737926A (en) * 1986-01-21 1988-04-12 Intel Corporation Optimally partitioned regenerative carry lookahead adder
US4882698A (en) * 1987-10-07 1989-11-21 Harris Corporation Cell based ALU with tree structured carry, inverting logic and balanced loading
US5047974A (en) * 1987-11-24 1991-09-10 Harris Corporation Cell based adder with tree structured carry, inverting logic and balanced loading
US4858168A (en) * 1988-02-16 1989-08-15 American Telephone And Telegraph Company Carry look-ahead technique having a reduced number of logic levels
WO1989008294A1 (en) * 1988-02-29 1989-09-08 Chopp Computer Corporation Carry generation method and apparatus
US5122982A (en) * 1988-02-29 1992-06-16 Chopp Computer Corporation Carry generation method and apparatus
US4885716A (en) * 1988-08-15 1989-12-05 Dallas Semiconductor Corporation High speed carry chain
US4905180A (en) * 1988-12-16 1990-02-27 Intel Corporation MOS adder with minimum pass gates in carry line
JPH02259926A (ja) * 1989-03-31 1990-10-22 Hitachi Ltd 加算制御方式
JPH04296933A (ja) * 1991-03-04 1992-10-21 Mitsubishi Electric Corp 半導体集積回路装置
US5257218A (en) * 1992-01-06 1993-10-26 Intel Corporation Parallel carry and carry propagation generator apparatus for use with carry-look-ahead adders
US5497343A (en) * 1993-08-05 1996-03-05 Hyundai Electronics America Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method
DE69626596T2 (de) * 1995-10-20 2003-12-18 Kabushiki Kaisha Toshiba, Kawasaki Logische Schaltung, die nach dem Carry select Prinzip arbeitet
US5926407A (en) * 1997-03-06 1999-07-20 Advanced Micro Devices, Inc. Combined add/shift structure
US6782406B2 (en) * 2001-06-07 2004-08-24 Koninklijke Philips Electronics N.V. Fast CMOS adder with null-carry look-ahead
DE10215784A1 (de) * 2002-04-10 2003-10-30 Infineon Technologies Ag Rechenwerk und Verfahren zum Subtrahieren
US7395294B1 (en) * 2003-01-10 2008-07-01 Altera Corporation Arithmetic logic unit
US7237216B2 (en) * 2003-02-21 2007-06-26 Infineon Technologies Ag Clock gating approach to accommodate infrequent additional processing latencies
GB0412084D0 (en) * 2004-05-29 2004-06-30 Univ Belfast "Method of calculating a modular inverse"

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3548177A (en) 1968-01-18 1970-12-15 Ibm Computer error anticipator and cycle extender
US3983538A (en) 1974-05-01 1976-09-28 International Business Machines Corporation Universal LSI array logic modules with integral storage array and variable autonomous sequencing
IT1038941B (it) 1974-07-06 1979-11-30 Ibm Sistema di calcolo perfezionato
US4105978A (en) 1976-08-02 1978-08-08 Honeywell Information Systems Inc. Stretch and stall clock
US4099248A (en) 1977-01-28 1978-07-04 Sperry Rand Corporation One's complement subtractive arithmetic unit utilizing two's complement arithmetic circuits
US4504924A (en) 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates

Also Published As

Publication number Publication date
EP0136939A2 (en) 1985-04-10
CA1216951A (en) 1987-01-20
US4623981A (en) 1986-11-18
EP0136939B1 (en) 1991-11-13
JPH0260004B2 (enrdf_load_stackoverflow) 1990-12-14
JPS60144825A (ja) 1985-07-31
EP0136939A3 (en) 1988-12-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee