DE3482529D1 - Nur-lesespeicher. - Google Patents

Nur-lesespeicher.

Info

Publication number
DE3482529D1
DE3482529D1 DE8484305083T DE3482529T DE3482529D1 DE 3482529 D1 DE3482529 D1 DE 3482529D1 DE 8484305083 T DE8484305083 T DE 8484305083T DE 3482529 T DE3482529 T DE 3482529T DE 3482529 D1 DE3482529 D1 DE 3482529D1
Authority
DE
Germany
Prior art keywords
read
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484305083T
Other languages
English (en)
Inventor
Yoshio Sakai
Ryo Nagai
Shuichi Yamamoto
Hideo Nakamura
Kouki Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3482529D1 publication Critical patent/DE3482529D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/927—Different doping levels in different parts of PN junction to produce shaped depletion layer

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE8484305083T 1983-07-29 1984-07-26 Nur-lesespeicher. Expired - Lifetime DE3482529D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58137537A JPS6030170A (ja) 1983-07-29 1983-07-29 高集積読み出し専用メモリ

Publications (1)

Publication Number Publication Date
DE3482529D1 true DE3482529D1 (de) 1990-07-19

Family

ID=15201000

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484305083T Expired - Lifetime DE3482529D1 (de) 1983-07-29 1984-07-26 Nur-lesespeicher.

Country Status (5)

Country Link
US (1) US4707718A (de)
EP (1) EP0133023B1 (de)
JP (1) JPS6030170A (de)
KR (1) KR920010196B1 (de)
DE (1) DE3482529D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0231271A1 (de) * 1985-07-29 1987-08-12 AT&T Corp. Verbindungsschema auf drei ebenen für integrierte schaltungen
JP2511485B2 (ja) * 1988-01-12 1996-06-26 沖電気工業株式会社 半導体記憶装置
JP2765583B2 (ja) * 1988-10-20 1998-06-18 株式会社リコー 半導体メモリ装置
JP2901188B2 (ja) * 1988-12-28 1999-06-07 株式会社東芝 半導体集積回路
US5301349A (en) * 1988-12-28 1994-04-05 Kabushiki Kaisha Toshiba Single chip computer having ground wire formed immediately parallel a data bus and drivers formed directly under the data bus for high speed data transfer
DE69027614T2 (de) * 1989-03-14 1996-11-28 Toshiba Kawasaki Kk Halbleitervorrichtung mit Mehrlagenverdrahtung und Verfahren zu ihrer Herstellung
JPH07114258B2 (ja) * 1989-09-13 1995-12-06 東芝マイクロエレクトロニクス株式会社 半導体メモリ
US5117389A (en) * 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
EP0558133B1 (de) * 1992-02-27 1997-06-18 Koninklijke Philips Electronics N.V. Integrierte CMOS-Schaltung
US5291435A (en) * 1993-01-07 1994-03-01 Yu Shih Chiang Read-only memory cell
US5380676A (en) * 1994-05-23 1995-01-10 United Microelectronics Corporation Method of manufacturing a high density ROM
TW583431B (en) * 2000-02-22 2004-04-11 Toshiba Corp Liquid crystal display device
US6646312B1 (en) * 2000-07-28 2003-11-11 Oki Electric Industry Co., Ltd. Semiconductor memory device with bit lines having reduced cross-talk
JP2003224212A (ja) * 2002-01-30 2003-08-08 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP4002453A4 (de) * 2020-05-28 2022-11-16 Changxin Memory Technologies, Inc. Ausleitstruktur für wortleitung und verfahren zu ihrer herstellung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51111020A (en) * 1975-03-26 1976-10-01 Hitachi Ltd Semiconductor fixing memory equipment
JPS54121685A (en) * 1978-03-14 1979-09-20 Kyushu Nippon Electric Ic and method of fabricating same
JPS5571063A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Semiconductor fixed memory
EP0014388B1 (de) * 1979-01-25 1983-12-21 Nec Corporation Halbleiterspeicher-Vorrichtung
US4282646A (en) * 1979-08-20 1981-08-11 International Business Machines Corporation Method of making a transistor array
JPS56150858A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device and manufacture thereof
JPS56157056A (en) * 1980-05-09 1981-12-04 Fujitsu Ltd Manufacture of read-only memory
EP0054102A3 (de) * 1980-12-11 1983-07-27 Rockwell International Corporation ROM-Zellen in sehr dichter Anordnung und Herstellungsverfahren
US4380866A (en) * 1981-05-04 1983-04-26 Motorola, Inc. Method of programming ROM by offset masking of selected gates
US4358889A (en) * 1981-05-28 1982-11-16 General Motors Corporation Process for making a late programming enhanced contact ROM
EP0087979B1 (de) * 1982-03-03 1989-09-06 Fujitsu Limited Halbleiter-Speichervorrichtung

Also Published As

Publication number Publication date
EP0133023A3 (en) 1986-07-02
EP0133023A2 (de) 1985-02-13
KR920010196B1 (ko) 1992-11-19
KR850000799A (ko) 1985-03-09
US4707718A (en) 1987-11-17
JPS6030170A (ja) 1985-02-15
EP0133023B1 (de) 1990-06-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee