DE3481559D1 - Eine, fuer eine arithmetische operation hoher geschwindigkeit geeignete, uebertragsschaltung. - Google Patents

Eine, fuer eine arithmetische operation hoher geschwindigkeit geeignete, uebertragsschaltung.

Info

Publication number
DE3481559D1
DE3481559D1 DE8484116331T DE3481559T DE3481559D1 DE 3481559 D1 DE3481559 D1 DE 3481559D1 DE 8484116331 T DE8484116331 T DE 8484116331T DE 3481559 T DE3481559 T DE 3481559T DE 3481559 D1 DE3481559 D1 DE 3481559D1
Authority
DE
Germany
Prior art keywords
transmission circuit
arithmetic operation
circuit suitable
speed arithmetic
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484116331T
Other languages
English (en)
Inventor
Kouichi C O Nec Corp Yamada
Masatoshi C O Nec Corp Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP25010583A external-priority patent/JPS60140426A/ja
Priority claimed from JP24700683A external-priority patent/JPS60140425A/ja
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3481559D1 publication Critical patent/DE3481559D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Logic Circuits (AREA)
DE8484116331T 1983-12-27 1984-12-27 Eine, fuer eine arithmetische operation hoher geschwindigkeit geeignete, uebertragsschaltung. Expired - Fee Related DE3481559D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP25010583A JPS60140426A (ja) 1983-12-27 1983-12-27 キヤリ−回路
JP24700683A JPS60140425A (ja) 1983-12-28 1983-12-28 キヤリ−回路

Publications (1)

Publication Number Publication Date
DE3481559D1 true DE3481559D1 (de) 1990-04-12

Family

ID=26538015

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484116331T Expired - Fee Related DE3481559D1 (de) 1983-12-27 1984-12-27 Eine, fuer eine arithmetische operation hoher geschwindigkeit geeignete, uebertragsschaltung.

Country Status (3)

Country Link
US (2) US4763295A (de)
EP (1) EP0164450B1 (de)
DE (1) DE3481559D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8531380D0 (en) * 1985-12-20 1986-02-05 Texas Instruments Ltd Multi-stage parallel binary adder
US4737926A (en) * 1986-01-21 1988-04-12 Intel Corporation Optimally partitioned regenerative carry lookahead adder
FR2596544B1 (fr) * 1986-03-28 1988-05-13 Radiotechnique Compelec Circuit arithmetique et logique
FR2596543B1 (fr) * 1986-03-28 1989-10-27 Radiotechnique Compelec Unite arithmetique et logique
EP0257362A1 (de) * 1986-08-27 1988-03-02 Siemens Aktiengesellschaft Addierer
JPH07120271B2 (ja) * 1987-04-28 1995-12-20 日本電気株式会社 算術論理装置
FR2628232B1 (fr) * 1988-03-07 1994-04-08 Etat Francais Cnet Additionneur de type recursif pour calculer la somme de deux operandes
JP2885402B2 (ja) * 1988-06-15 1999-04-26 富士通株式会社 並列形全加算器の桁上げ伝搬回路
US4982357A (en) * 1989-04-28 1991-01-01 International Business Machines Corporation Plural dummy select chain logic synthesis network
US5301341A (en) * 1990-11-28 1994-04-05 International Business Machines Corporation Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions
US5163019A (en) * 1990-11-29 1992-11-10 Brooktree Corporation Binary carry circuitry
US5146424A (en) * 1991-11-21 1992-09-08 Unisys Corporation Digital adder having a high-speed low-capacitance carry bypass signal path
EP0590251A2 (de) * 1992-09-22 1994-04-06 Motorola, Inc. Hochgeschwindigkeitsaddierer
KR0137969Y1 (ko) * 1993-03-26 1999-04-01 문정환 캐리전달회로
KR950004225B1 (ko) * 1993-04-16 1995-04-27 현대전자산업주식회사 고속 캐리 증가 가산기
GB2342193B (en) 1998-06-19 2003-06-04 Sgs Thomson Microelectronics Addition circuitry
US20060277243A1 (en) * 2005-06-02 2006-12-07 International Business Machines Corporation Alternate representation of integers for efficient implementation of addition of a sequence of multiprecision integers

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553446A (en) * 1966-08-04 1971-01-05 Honeywell Inc Carry determination logic
US3717755A (en) * 1971-05-21 1973-02-20 Bell Telephone Labor Inc Parallel adder using a carry propagation bus
US3728532A (en) * 1972-01-21 1973-04-17 Rca Corp Carry skip-ahead network
US3843876A (en) * 1973-09-20 1974-10-22 Motorola Inc Electronic digital adder having a high speed carry propagation line
US4031379A (en) * 1976-02-23 1977-06-21 Intel Corporation Propagation line adder and method for binary addition
US4152775A (en) * 1977-07-20 1979-05-01 Intel Corporation Single line propagation adder and method for binary addition
US4425623A (en) * 1981-07-14 1984-01-10 Rockwell International Corporation Lookahead carry circuit apparatus
DE3138991A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Digitales rechenwerk und verfahren zu seinem betrieb
US4504924A (en) * 1982-06-28 1985-03-12 International Business Machines Corporation Carry lookahead logical mechanism using affirmatively referenced transfer gates

Also Published As

Publication number Publication date
EP0164450B1 (de) 1990-03-07
EP0164450A3 (en) 1986-04-23
US4845655A (en) 1989-07-04
EP0164450A2 (de) 1985-12-18
US4763295A (en) 1988-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee