FR2596543B1 - Unite arithmetique et logique - Google Patents

Unite arithmetique et logique

Info

Publication number
FR2596543B1
FR2596543B1 FR8604507A FR8604507A FR2596543B1 FR 2596543 B1 FR2596543 B1 FR 2596543B1 FR 8604507 A FR8604507 A FR 8604507A FR 8604507 A FR8604507 A FR 8604507A FR 2596543 B1 FR2596543 B1 FR 2596543B1
Authority
FR
France
Prior art keywords
arithmetic
logic unit
logic
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8604507A
Other languages
English (en)
Other versions
FR2596543A1 (fr
Inventor
Michel Lanfranca
Jean-Michel Labrousse
Christian Deneuchatel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Radiotechnique Compelec RTC SA
Original Assignee
Radiotechnique Compelec RTC SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radiotechnique Compelec RTC SA filed Critical Radiotechnique Compelec RTC SA
Priority to FR8604507A priority Critical patent/FR2596543B1/fr
Publication of FR2596543A1 publication Critical patent/FR2596543A1/fr
Application granted granted Critical
Publication of FR2596543B1 publication Critical patent/FR2596543B1/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3872Precharge of output to prevent leakage

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
FR8604507A 1986-03-28 1986-03-28 Unite arithmetique et logique Expired FR2596543B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8604507A FR2596543B1 (fr) 1986-03-28 1986-03-28 Unite arithmetique et logique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8604507A FR2596543B1 (fr) 1986-03-28 1986-03-28 Unite arithmetique et logique

Publications (2)

Publication Number Publication Date
FR2596543A1 FR2596543A1 (fr) 1987-10-02
FR2596543B1 true FR2596543B1 (fr) 1989-10-27

Family

ID=9333666

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8604507A Expired FR2596543B1 (fr) 1986-03-28 1986-03-28 Unite arithmetique et logique

Country Status (1)

Country Link
FR (1) FR2596543B1 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3100835A (en) * 1960-01-06 1963-08-13 Ibm Selecting adder
EP0164450B1 (fr) * 1983-12-27 1990-03-07 Nec Corporation Circuit de retenue apte à une opération arithmétique rapide

Also Published As

Publication number Publication date
FR2596543A1 (fr) 1987-10-02

Similar Documents

Publication Publication Date Title
IT1205010B (it) Tetraidronaftalin-derivati e indan-derivati
DK377487A (da) P-aminophenolderivater
DE68928959D1 (de) Logik-Schaltungsanordnungen
DK254488D0 (da) Azaindol- og indolizinderivater
DK332587A (da) Transparent saebe samt fremstilling deraf
DE69030337T2 (de) Register- und Arithmetische-Logik-Einheit
IT1221969B (it) Registro asincrono ad ingressi mutlipli
FR2596544B1 (fr) Circuit arithmetique et logique
FI883607A0 (fi) Effektivt foerfarande foer in vitro-in vivo-produktion av minirotknoelar av potatis.
FR2596543B1 (fr) Unite arithmetique et logique
TR24875A (tr) Fungusidlerde veya bunlarla ilgili islahat
FI881648A (fi) Shampookoostumuksia
BR8601118A (pt) Imantador e desimantador
ES1004213Y (es) Nuevos nichos e hipogeos
DK428987D0 (da) En fallelaas
ES285631Y (es) Pasatiempo aritmetico
BR6601822U (pt) Disposicao introduzida em funil
BR6602192U (pt) Disposicao introduzida em mamadeira
BR6601178U (pt) Disposicao introduzida em dobradica
BR6601884U (pt) Disposicao introduzida em guarda-sol
BR6601062U (pt) Disposicao introduzida em cambao
BR6602394U (pt) Disposicao introduzida em palmilha
BR6601821U (pt) Disposicao introduzida em chinelo
BR6601780U (pt) Disposicao introduzida em ratoeira
BR6600597U (pt) Disposicao introduzida em cremogenador

Legal Events

Date Code Title Description
CD Change of name or company name
CD Change of name or company name
ST Notification of lapse