DE3410196A1 - Leiterband fuer die montage von integrierten schaltkreisen - Google Patents

Leiterband fuer die montage von integrierten schaltkreisen

Info

Publication number
DE3410196A1
DE3410196A1 DE19843410196 DE3410196A DE3410196A1 DE 3410196 A1 DE3410196 A1 DE 3410196A1 DE 19843410196 DE19843410196 DE 19843410196 DE 3410196 A DE3410196 A DE 3410196A DE 3410196 A1 DE3410196 A1 DE 3410196A1
Authority
DE
Germany
Prior art keywords
island
webs
frame
longitudinal axis
tape according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19843410196
Other languages
German (de)
English (en)
Other versions
DE3410196C2 (cs
Inventor
Albert Dipl.-Ing. Walther (FH), 8150 Holzkirchen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to DE19843410196 priority Critical patent/DE3410196A1/de
Publication of DE3410196A1 publication Critical patent/DE3410196A1/de
Application granted granted Critical
Publication of DE3410196C2 publication Critical patent/DE3410196C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Packaging Frangible Articles (AREA)
  • Elimination Of Static Electricity (AREA)
DE19843410196 1984-03-20 1984-03-20 Leiterband fuer die montage von integrierten schaltkreisen Granted DE3410196A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19843410196 DE3410196A1 (de) 1984-03-20 1984-03-20 Leiterband fuer die montage von integrierten schaltkreisen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19843410196 DE3410196A1 (de) 1984-03-20 1984-03-20 Leiterband fuer die montage von integrierten schaltkreisen

Publications (2)

Publication Number Publication Date
DE3410196A1 true DE3410196A1 (de) 1985-09-26
DE3410196C2 DE3410196C2 (cs) 1993-03-11

Family

ID=6231068

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843410196 Granted DE3410196A1 (de) 1984-03-20 1984-03-20 Leiterband fuer die montage von integrierten schaltkreisen

Country Status (1)

Country Link
DE (1) DE3410196A1 (cs)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0213014A1 (en) * 1985-07-23 1987-03-04 Fairchild Semiconductor Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
US4796080A (en) * 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
EP0300632A3 (en) * 1987-07-20 1990-12-12 Gennum Corporation Plastic encapsulated integrated circuit package with electrostatic shield

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2630695A1 (de) * 1975-07-24 1977-02-10 Telcon Metals Ltd Halbleitervorrichtung
US4177480A (en) * 1975-10-02 1979-12-04 Licentia Patent-Verwaltungs-G.M.B.H. Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads
DE3130072A1 (de) * 1981-01-12 1982-08-05 AVX Corp., n. d. Ges. d. Staates Delaware, 11022 Great Neck, N.Y. Integriertes schaltglied
EP0086724A2 (en) * 1982-02-16 1983-08-24 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Integrated circuit lead frame with improved power dissipation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2630695A1 (de) * 1975-07-24 1977-02-10 Telcon Metals Ltd Halbleitervorrichtung
US4177480A (en) * 1975-10-02 1979-12-04 Licentia Patent-Verwaltungs-G.M.B.H. Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads
DE3130072A1 (de) * 1981-01-12 1982-08-05 AVX Corp., n. d. Ges. d. Staates Delaware, 11022 Great Neck, N.Y. Integriertes schaltglied
EP0086724A2 (en) * 1982-02-16 1983-08-24 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Integrated circuit lead frame with improved power dissipation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0213014A1 (en) * 1985-07-23 1987-03-04 Fairchild Semiconductor Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate
EP0300632A3 (en) * 1987-07-20 1990-12-12 Gennum Corporation Plastic encapsulated integrated circuit package with electrostatic shield
US4796080A (en) * 1987-07-23 1989-01-03 Fairchild Camera And Instrument Corporation Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate

Also Published As

Publication number Publication date
DE3410196C2 (cs) 1993-03-11

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee