DE3377439T2 - - Google Patents
Info
- Publication number
- DE3377439T2 DE3377439T2 DE19833377439 DE3377439T DE3377439T2 DE 3377439 T2 DE3377439 T2 DE 3377439T2 DE 19833377439 DE19833377439 DE 19833377439 DE 3377439 T DE3377439 T DE 3377439T DE 3377439 T2 DE3377439 T2 DE 3377439T2
- Authority
- DE
- Germany
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0813—Non-interconnected multi-emitter structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57059155A JPS58176932A (ja) | 1982-04-09 | 1982-04-09 | 縦型半導体素子の製造方法 |
JP57059940A JPS58176933A (ja) | 1982-04-10 | 1982-04-10 | 縦型半導体素子の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3377439D1 DE3377439D1 (en) | 1988-08-25 |
DE3377439T2 true DE3377439T2 (de) | 1988-08-25 |
Family
ID=26400200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383103249T Expired DE3377439D1 (en) | 1982-04-09 | 1983-03-31 | Method of manufacturing vertical semiconductor devices |
Country Status (3)
Country | Link |
---|---|
US (1) | US4488349A (de) |
EP (1) | EP0091624B1 (de) |
DE (1) | DE3377439D1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3435571A1 (de) * | 1984-09-27 | 1986-04-10 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierte bipolare darlington-schaltung |
FR2581481B1 (fr) * | 1985-05-03 | 1988-04-29 | Radiotechnique Compelec | Transistor hyperfrequences et son procede de fabrication |
AT384737B (de) * | 1986-04-04 | 1987-12-28 | Thoma Dipl Ing Dr Techn Herwig | Vorrichtung zur stroemungskonstanten abgabe fluessiger arzneimittel |
US5055416A (en) * | 1988-12-07 | 1991-10-08 | Minnesota Mining And Manufacturing Company | Electrolytic etch for preventing electrical shorts in solar cells on polymer surfaces |
US6039857A (en) * | 1998-11-09 | 2000-03-21 | Yeh; Ching-Fa | Method for forming a polyoxide film on doped polysilicon by anodization |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3851245A (en) * | 1973-12-26 | 1974-11-26 | Ibm | Method for determining whether holes in insulated layer of semiconductor substrate are fully open |
GB1503411A (en) * | 1976-01-16 | 1978-03-08 | Nat Res Dev | Gaas mosfet |
US4045310A (en) * | 1976-05-03 | 1977-08-30 | Teletype Corporation | Starting product for the production of a read-only memory and a method of producing it and the read-only memory |
US4104090A (en) * | 1977-02-24 | 1978-08-01 | International Business Machines Corporation | Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation |
GB2038548B (en) * | 1978-10-27 | 1983-03-23 | Nippon Telegraph & Telephone | Isolating semiconductor device by porous silicon oxide |
US4158613A (en) * | 1978-12-04 | 1979-06-19 | Burroughs Corporation | Method of forming a metal interconnect structure for integrated circuits |
US4242791A (en) * | 1979-09-21 | 1981-01-06 | International Business Machines Corporation | High performance bipolar transistors fabricated by post emitter base implantation process |
FR2470444A1 (fr) * | 1979-11-21 | 1981-05-29 | Radiotechnique Compelec | Perfectionnement au procede de realisation d'un reseau de connexions par anodisation localisee sur un support semi-conducteur |
JPS5687346A (en) * | 1979-12-18 | 1981-07-15 | Nec Corp | Manufacture of semiconductor device |
US4420497A (en) * | 1981-08-24 | 1983-12-13 | Fairchild Camera And Instrument Corporation | Method of detecting and repairing latent defects in a semiconductor dielectric layer |
-
1983
- 1983-03-15 US US06/475,403 patent/US4488349A/en not_active Expired - Fee Related
- 1983-03-31 EP EP83103249A patent/EP0091624B1/de not_active Expired
- 1983-03-31 DE DE8383103249T patent/DE3377439D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4488349A (en) | 1984-12-18 |
EP0091624A3 (en) | 1985-07-03 |
EP0091624B1 (de) | 1988-07-20 |
EP0091624A2 (de) | 1983-10-19 |
DE3377439D1 (en) | 1988-08-25 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN |
|
8339 | Ceased/non-payment of the annual fee |