DE3361888D1 - Clock driver - Google Patents

Clock driver

Info

Publication number
DE3361888D1
DE3361888D1 DE8383102359T DE3361888T DE3361888D1 DE 3361888 D1 DE3361888 D1 DE 3361888D1 DE 8383102359 T DE8383102359 T DE 8383102359T DE 3361888 T DE3361888 T DE 3361888T DE 3361888 D1 DE3361888 D1 DE 3361888D1
Authority
DE
Germany
Prior art keywords
clock driver
clock
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383102359T
Other languages
English (en)
Inventor
Daniel J Kouba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3361888D1 publication Critical patent/DE3361888D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
DE8383102359T 1982-06-14 1983-03-10 Clock driver Expired DE3361888D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/387,990 US4477738A (en) 1982-06-14 1982-06-14 LSSD Compatible clock driver

Publications (1)

Publication Number Publication Date
DE3361888D1 true DE3361888D1 (en) 1986-03-06

Family

ID=23532162

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383102359T Expired DE3361888D1 (en) 1982-06-14 1983-03-10 Clock driver

Country Status (4)

Country Link
US (1) US4477738A (de)
EP (1) EP0096167B1 (de)
JP (1) JPS58221178A (de)
DE (1) DE3361888D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119917A (ja) * 1982-12-27 1984-07-11 Toshiba Corp 論理回路
US4896054A (en) * 1983-08-01 1990-01-23 International Business Machines Corporation Optional single or double clocked latch
US4580137A (en) * 1983-08-29 1986-04-01 International Business Machines Corporation LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control
US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
US4625127A (en) * 1984-08-06 1986-11-25 Advanced Micro Devices, Inc. High-fanout clock driver for low level gates
US4697241A (en) * 1985-03-01 1987-09-29 Simulog, Inc. Hardware logic simulator
JP2689416B2 (ja) * 1986-08-18 1997-12-10 日本電気株式会社 フリツプフロツプ
JPS63110811A (ja) * 1986-10-28 1988-05-16 Mitsubishi Electric Corp クロツクジエネレ−タ
US4797575A (en) * 1986-12-05 1989-01-10 Western Digital Corporation Flip-flop with identical propagation delay in clock pass through mode and in normal operation
JP2570471B2 (ja) * 1990-06-25 1997-01-08 日本電気株式会社 クロックドライバー回路
US6629277B1 (en) 2000-02-15 2003-09-30 Sun Microsystems, Inc. LSSD interface
KR100526350B1 (ko) * 2003-08-23 2005-11-08 삼성전자주식회사 다상 클록신호 발생회로 및 방법
CN102832924B (zh) * 2012-09-12 2015-02-25 中国电子科技集团公司第二十四研究所 大功率lvds方波信号驱动电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815025A (en) * 1971-10-18 1974-06-04 Ibm Large-scale integrated circuit testing structure
CA961933A (en) * 1972-09-26 1975-01-28 Microsystems International Limited Bi-directional amplifying bus-switch
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3965459A (en) * 1974-04-01 1976-06-22 Rockwell International Selectable eight or twelve digit integrated circuit calculator and conditional gate output signal modification circuit therefor
US3882390A (en) * 1974-07-31 1975-05-06 Bell Telephone Labor Inc Flip-flop balance testing circuit
US4063078A (en) * 1976-06-30 1977-12-13 International Business Machines Corporation Clock generation network for level sensitive logic system
US4035663A (en) * 1976-09-01 1977-07-12 Rockwell International Corporation Two phase clock synchronizing method and apparatus
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit
US4241307A (en) * 1978-08-18 1980-12-23 International Business Machines Corporation Module interconnection testing scheme
US4315167A (en) * 1979-09-10 1982-02-09 International Business Machines Corporation Self-switching bidirectional digital line driver

Also Published As

Publication number Publication date
US4477738A (en) 1984-10-16
JPS58221178A (ja) 1983-12-22
EP0096167A1 (de) 1983-12-21
EP0096167B1 (de) 1986-01-22
JPS6323508B2 (de) 1988-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee