DE3328405C2 - - Google Patents

Info

Publication number
DE3328405C2
DE3328405C2 DE19833328405 DE3328405A DE3328405C2 DE 3328405 C2 DE3328405 C2 DE 3328405C2 DE 19833328405 DE19833328405 DE 19833328405 DE 3328405 A DE3328405 A DE 3328405A DE 3328405 C2 DE3328405 C2 DE 3328405C2
Authority
DE
Germany
Prior art keywords
bic
bus
interface circuit
csb
bas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19833328405
Other languages
German (de)
English (en)
Other versions
DE3328405A1 (de
Inventor
Klaus Dipl.-Ing. 8000 Muenchen De Jung
Rudi Dipl.-Phys. Dr. 8038 Groebenzell De Mueller
Hermann Dipl.-Ing. Reichbauer
Helmut Dipl.-Ing. 8000 Muenchen De Schneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19833328405 priority Critical patent/DE3328405A1/de
Publication of DE3328405A1 publication Critical patent/DE3328405A1/de
Application granted granted Critical
Publication of DE3328405C2 publication Critical patent/DE3328405C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
DE19833328405 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems Granted DE3328405A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19833328405 DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833328405 DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Publications (2)

Publication Number Publication Date
DE3328405A1 DE3328405A1 (de) 1985-02-21
DE3328405C2 true DE3328405C2 (fi) 1992-01-30

Family

ID=6205936

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833328405 Granted DE3328405A1 (de) 1983-08-05 1983-08-05 Steuerorgane eines fehlertoleranten mehrrechnersystems

Country Status (1)

Country Link
DE (1) DE3328405A1 (fi)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19509558A1 (de) * 1995-03-16 1996-09-19 Abb Patent Gmbh Verfahren zur fehlertoleranten Kommunikation unter hohen Echtzeitbedingungen
DE10325069B4 (de) * 2002-06-07 2012-05-24 Omron Corporation Programmierbare Steuerung mit CPU-Einheiten und Spezialfunktionsmodulen sowie Verfahren zur Aufdopplung

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH675781A5 (fi) * 1987-04-16 1990-10-31 Bbc Brown Boveri & Cie
FR2615341B1 (fr) * 1987-05-15 1993-12-03 Thomson Csf Systeme de commutation numerique
EP0306211A3 (en) * 1987-09-04 1990-09-26 Digital Equipment Corporation Synchronized twin computer system
US4907228A (en) * 1987-09-04 1990-03-06 Digital Equipment Corporation Dual-rail processor with error checking at single rail interfaces
CA1320276C (en) * 1987-09-04 1993-07-13 William F. Bruckert Dual rail processors with error checking on i/o reads
US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
US5153881A (en) * 1989-08-01 1992-10-06 Digital Equipment Corporation Method of handling errors in software
US5068780A (en) * 1989-08-01 1991-11-26 Digital Equipment Corporation Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
US5251227A (en) * 1989-08-01 1993-10-05 Digital Equipment Corporation Targeted resets in a data processor including a trace memory to store transactions
US5193181A (en) * 1990-10-05 1993-03-09 Bull Hn Information Systems Inc. Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
GB2268817B (en) * 1992-07-17 1996-05-01 Integrated Micro Products Ltd A fault-tolerant computer system
IT1255618B (it) * 1992-09-30 1995-11-09 Sits Soc It Telecom Siemens Unita' di controllo e di elaborazione duplicata per apparati di telecomunicazioni
DE9312739U1 (de) * 1993-08-25 1993-10-07 Siemens AG, 80333 München Redundantes Automatisierungssystem
FR2737029B1 (fr) * 1995-07-19 1997-09-26 Sextant Avionique Dispositif d'interface entre un calculateur a architecture redondante et un moyen de communication
US5754865A (en) * 1995-12-18 1998-05-19 International Business Machines Corporation Logical address bus architecture for multiple processor systems
DE19841183C2 (de) * 1998-09-09 2000-08-10 Daimler Chrysler Ag Vorrichtung zur Kopplung von redundanten elektronischen Schaltungen über redunante Busse ohne Fehlerfortpflanzung
DE10105707A1 (de) * 2001-02-08 2002-09-05 Siemens Ag Verfahren und Vorrichtung zur Datenübertragung
DE102009000045A1 (de) * 2009-01-07 2010-07-08 Robert Bosch Gmbh Verfahren und Vorrichtung zum Betreiben eines Steuergerätes
CN117215177A (zh) * 2023-11-09 2023-12-12 北京控制工程研究所 一种天地往返一体化控制系统及控制方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2113935A1 (de) * 1971-03-23 1972-10-05 Licentia Gmbh Anordnung fuer ein Mehrrechnersystem
US4245344A (en) * 1979-04-02 1981-01-13 Rockwell International Corporation Processing system with dual buses

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19509558A1 (de) * 1995-03-16 1996-09-19 Abb Patent Gmbh Verfahren zur fehlertoleranten Kommunikation unter hohen Echtzeitbedingungen
DE10325069B4 (de) * 2002-06-07 2012-05-24 Omron Corporation Programmierbare Steuerung mit CPU-Einheiten und Spezialfunktionsmodulen sowie Verfahren zur Aufdopplung

Also Published As

Publication number Publication date
DE3328405A1 (de) 1985-02-21

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Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: G06F 11/16

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee