DE3279917D1 - Method for producing semiconductor devices including the use of reactive ion etching - Google Patents

Method for producing semiconductor devices including the use of reactive ion etching

Info

Publication number
DE3279917D1
DE3279917D1 DE8282105210T DE3279917T DE3279917D1 DE 3279917 D1 DE3279917 D1 DE 3279917D1 DE 8282105210 T DE8282105210 T DE 8282105210T DE 3279917 T DE3279917 T DE 3279917T DE 3279917 D1 DE3279917 D1 DE 3279917D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
reactive ion
ion etching
devices including
producing semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282105210T
Other languages
English (en)
Inventor
Narasipur Gundappa Anantha
Harsaran Singh Bhatia
Iv John Lester Mauer
Homi Gustadji Sarkary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3279917D1 publication Critical patent/DE3279917D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
DE8282105210T 1981-06-30 1982-06-15 Method for producing semiconductor devices including the use of reactive ion etching Expired DE3279917D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/279,129 US4389294A (en) 1981-06-30 1981-06-30 Method for avoiding residue on a vertical walled mesa

Publications (1)

Publication Number Publication Date
DE3279917D1 true DE3279917D1 (en) 1989-10-05

Family

ID=23067742

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282105210T Expired DE3279917D1 (en) 1981-06-30 1982-06-15 Method for producing semiconductor devices including the use of reactive ion etching

Country Status (4)

Country Link
US (1) US4389294A (de)
EP (1) EP0068275B1 (de)
JP (1) JPS589338A (de)
DE (1) DE3279917D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562127B1 (de) * 1991-10-14 2001-04-25 Denso Corporation Verfahren zur Herstellung einer Halbleiteranordnung
US5521422A (en) * 1994-12-02 1996-05-28 International Business Machines Corporation Corner protected shallow trench isolation device
KR100216267B1 (ko) * 1996-12-26 1999-08-16 구본준 트렌치 격리구조를 갖는 반도체 장치 제조방법
US5804490A (en) * 1997-04-14 1998-09-08 International Business Machines Corporation Method of filling shallow trenches
JP3252780B2 (ja) * 1998-01-16 2002-02-04 日本電気株式会社 シリコン層のエッチング方法
US6221733B1 (en) * 1998-11-13 2001-04-24 Lattice Semiconductor Corporation Reduction of mechanical stress in shallow trench isolation process
US6159821A (en) * 1999-02-12 2000-12-12 Vanguard International Semiconductor Corporation Methods for shallow trench isolation
US6232203B1 (en) * 1999-07-23 2001-05-15 Taiwan Semiconductor Manufacturing Company Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches
US6198140B1 (en) 1999-09-08 2001-03-06 Denso Corporation Semiconductor device including several transistors and method of manufacturing the same
US6096623A (en) * 1999-09-09 2000-08-01 United Semiconductor Corp. Method for forming shallow trench isolation structure
WO2001063663A1 (en) * 2000-02-24 2001-08-30 Advanced Micro Devices, Inc. Enhanced planarity isolation structure and method
FR2806834B1 (fr) * 2000-03-24 2003-09-12 St Microelectronics Sa Procede de formation de zone isolante
JP4068286B2 (ja) 2000-06-30 2008-03-26 株式会社東芝 半導体装置の製造方法
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3880684A (en) * 1973-08-03 1975-04-29 Mitsubishi Electric Corp Process for preparing semiconductor
US3918149A (en) * 1974-06-28 1975-11-11 Intel Corp Al/Si metallization process
JPS5249772A (en) * 1975-10-18 1977-04-21 Hitachi Ltd Process for production of semiconductor device
GB1485015A (en) * 1974-10-29 1977-09-08 Mullard Ltd Semi-conductor device manufacture
US4117301A (en) * 1975-07-21 1978-09-26 Rca Corporation Method of making a submicrometer aperture in a substrate
JPS5226182A (en) * 1975-08-25 1977-02-26 Hitachi Ltd Manufacturing method of semi-conductor unit
US4035276A (en) * 1976-04-29 1977-07-12 Ibm Corporation Making coplanar layers of thin films
US4076680A (en) * 1976-08-05 1978-02-28 Allied Chemical Corporation Poly(hydroxymethylene) solutions
JPS5328530A (en) * 1976-08-30 1978-03-16 Hitachi Ltd Method of etching surfaces of solids
JPS6047738B2 (ja) * 1977-09-14 1985-10-23 松下電器産業株式会社 半導体装置のコンタクト形成方法
US4181564A (en) * 1978-04-24 1980-01-01 Bell Telephone Laboratories, Incorporated Fabrication of patterned silicon nitride insulating layers having gently sloping sidewalls
US4135998A (en) * 1978-04-26 1979-01-23 International Business Machines Corp. Method for forming pt-si schottky barrier contact
US4307180A (en) * 1980-08-22 1981-12-22 International Business Machines Corp. Process of forming recessed dielectric regions in a monocrystalline silicon substrate
US4326936A (en) * 1980-10-14 1982-04-27 Rockwell International Corporation Repeatable method for sloping walls of thin film material

Also Published As

Publication number Publication date
EP0068275B1 (de) 1989-08-30
JPH0371781B2 (de) 1991-11-14
JPS589338A (ja) 1983-01-19
EP0068275A3 (en) 1986-10-01
US4389294A (en) 1983-06-21
EP0068275A2 (de) 1983-01-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee